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參數(shù)資料
| 型號： | IS41LV82052 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 2M x 8 DRAM With Fast Page Mode(3.3V,2M x 8 帶快速頁模式動態(tài)RAM(刷新 2K）) |
| 中文描述： | 200萬× 8的DRAM與快速頁面模式（3.3伏，200萬× 8帶快速頁模式動態(tài)隨機存儲器（刷新2k）的） |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 170K |
| 代理商： | IS41LV82052 |
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
3
IS41C82052
IS41LV82052
ISSI
Functional Description
The IS41C82052 and IS41LV82052 are CMOS DRAMs
optimized for
high-speed bandwidth, low power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 11 address bits. These are entered
11 bits (A0-A10) at a time. The row address is latched by
the Row Address Strobe (
RAS
). The column address is
latched by the Column Address Strobe (
CAS
).
RAS
is
used to latch the first nine bits and
CAS
is used the latter
ten bits.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE
,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time specified
by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE
, whichever occurs last. The input data must be valid
at or before the falling edge of
CAS
or
WE
, whichever
occurs last.
Auto Refresh Cycle
To retain data, 2,048 refresh cycles are required in each
32 ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) with RAS at least once every 32 ms. Any
read, write,
read-modify-write
or
RAS-only
cycle refreshes
the addressed row.
2. Using a
CAS
-before-
RAS
refresh cycle.
CAS
-before-
RAS
refresh is activated by the falling edge of
RAS
, while
holding
CAS
LOW. In
CAS
-before-
RAS
refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
CAS
-before-
RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the V
CC
supply, an initial pause of
200 μs is required followed by a minimum of eight
initialization cycles (any combination of cycles contain-
ing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IS41LV82052-50J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Fast Page Mode DRAM |
| IS41LV82052-50JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Fast Page Mode DRAM |
| IS41LV82052-50T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Fast Page Mode DRAM |
| IS41LV82052-50TI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Fast Page Mode DRAM |
| IS41LV82052-60J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Fast Page Mode DRAM |
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