參數(shù)資料
型號(hào): IS42S32200B-7T
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 2M X 32 SYNCHRONOUS DRAM, 6.5 ns, PDSO86
封裝: 0.400 INCH, PLASTIC, TSOP2-86
文件頁數(shù): 34/56頁
文件大?。?/td> 537K
代理商: IS42S32200B-7T
IS42S32200B
ISSI
34
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00C
09/29/03
AC ELECTRICAL CHARACTERISTICS
(1,2,3)
-6
-7
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
t
DPL3
Input Data To Precharge
Command Delay time
CAS
Latency = 3
2CLK
2CLK
ns
t
DPL2
CAS
Latency = 2
2CLK
2CLK
ns
t
DAL3
Input Data To Active / Refresh
CAS
Latency = 3
Command Delay time (During Auto-Precharge)
2CLK+t
RP
2CLK+t
RP
ns
t
DAL2
CAS
Latency = 2
2CLK+t
RP
2CLK+t
RP
ns
t
T
Transition Time
(2)
0.3
1.2
0.3
1.2
ns
t
WR
Write Recovery Time
1CLK+6ns
1CLK+7ns
t
CK
t
XSR
Exit Self Refresh and Active Command
(6)
70
70
ns
t
RFC
Auto Refresh Period
60
70
ns
t
REF
Notes:
1. An initial pause of 100us is required after power up, followed by two AUTO REFRESH commands, before proper device operation
is ensured. (Vdd and VddQ must be powered up simultaneously. GND and GNDQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated anytime the t
REF
refresh requirement is exceeded.
2. Measured with t
T
= 1 ns.
3. The reference level is 1.5V when measuring input signal timing. Rise/fall times are measured between V
IH
(min.) and V
IL
(max.).
6. CLK must be toggled a minimum of two times during this period.
Refresh Cycle Time (4096)
64
64
ms
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IS42S32200B-7TL 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200B-7TLI 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
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