參數(shù)資料
型號(hào)： IS42VS16400C1-10TL
廠(chǎng)商： INTEGRATED SILICON SOLUTION INC
元件分類(lèi)： DRAM
英文描述： 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述： 4M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO54
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54
文件頁(yè)數(shù)： 14/56頁(yè)
文件大?。?/td> 509K
代理商： IS42VS16400C1-10TL
IS42VS16400C1
ISSI
14
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
10/06/05
AC CHARACTERISTICS
(1,2,3,6)
-10
-12
Symbol Parameter
Min.
Max.
Min.
Max.
Units
t
CK
3
t
CK
2
Clock Cycle Time
CAS
Latency = 3
CAS
Latency = 2
10
12
—
—
12
15
—
—
ns
ns
t
AC
3
t
AC
2
Access Time From CLK
(4)
CAS
Latency = 3
CAS
Latency = 2
—
—
8
9
—
—
9
ns
ns
10
t
CHI
CLK HIGH Level Width
3
—
3
—
ns
t
CL
CLK LOW Level Width
3
—
3
—
ns
t
OH
3
t
OH
2
Output Data Hold Time
CAS
Latency = 3
CAS
Latency = 2
2
2
—
—
2
2
—
—
ns
ns
t
LZ
Output LOW Impedance Time
0
—
0
—
ns
t
HZ
3
t
HZ
2
Output HIGH Impedance Time
(5)
CAS
Latency = 3
CAS
Latency = 2
—
—
8
9
—
—
9
ns
ns
10
t
DS
Input Data Setup Time
2
—
2
—
ns
t
DH
Input Data Hold Time
1
—
1
—
ns
t
AS
Address Setup Time
3
—
3
—
ns
t
AH
Address Hold Time
1
—
1
—
ns
t
CKS
CKE Setup Time
3
—
3
—
ns
t
CKH
CKE Hold Time
1
—
1
—
ns
t
CKA
CKE to CLK Recovery Delay Time
1CLK+3 —
1CLK+3
—
ns
t
CS
Command Setup Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
3
—
3
—
ns
t
CH
Command Hold Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
1
—
1
—
ns
t
RC
Command Period (REF to REF / ACT to ACT)
94
—
94
—
ns
t
RAS
Command Period (ACT to PRE)
50 100,000
50
100,000
ns
t
RP
Command Period (PRE to ACT)
30
—
30
—
ns
t
RCD
Active Command To Read / Write Command Delay Time
30
—
30
—
ns
t
RRD
Command Period (ACT [0] to ACT[1])
18
—
18
—
ns
t
DPL
3
Input Data To Precharge
Command Delay time
CAS
Latency = 3
2CLK
—
2CLK
—
ns
t
DPL
2
CAS
Latency = 2
2CLK
—
2CLK
—
ns
t
DAL
3
Input Data To Active / Refresh
Command Delay time (During Auto-Precharge)
CAS
Latency = 3
2CLK+t
RP
—
2CLK+t
RP
—
ns
t
DAL
2
CAS
Latency = 2
2CLK+t
RP
—
2CLK+t
RP
—
ns
t
T
Transition Time
0.5
5
0.5
5
ns
t
REF
Refresh Cycle Time (4096)
—
64
—
64
ms
Notes:
1. Thepower-on sequence must be executed before starting memory operation.
2. Measured with t
T
= 0.5 ns.
3. The reference level is 0.9V when measuring input signal timing. Rise and fall times are measured between V
IH
(min.) and V
IL
(max.).
4. Access time is measured at 0.9V with the load shown in the figure below.
5. The time t
HZ
(max.) is defined as the time required for the output voltage to become high impedance.
6.
Not all parameters are tested at the wafer level, but the parameters have been characterized previously.
相關(guān)PDF資料
PDF描述
IS42VS16400C1-10TLI 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-12T 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-12TI 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-12TL 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-12TLI 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS42VS16400C1-10TLI 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-12T 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-12TI 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-12TL 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42VS16400C1-12TLI 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
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