參數資料
型號: IS42VS16400C1-12TLI
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 4M X 16 SYNCHRONOUS DRAM, 9 ns, PDSO54
封裝: 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54
文件頁數: 17/56頁
文件大小: 509K
代理商: IS42VS16400C1-12TLI
IS42VS16400C1
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
10/06/05
17
REGISTER DEFINITION
Mode Register
The mode register is used to define the specific mode of
operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, an
operating mode and a write burst mode, as shown in MODE
REGISTER DEFINITION.
The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
until it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst
(sequential or interleaved)
, M4- M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 are reserved for future use.
The mode register must be loaded when all banks are idle,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either of
these requirements will result in unspecified operation.
MODE REGISTER DEFINITION
Latency Mode
M6 M5 M4
0
0
0
0
1
1
1
1
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1. To ensure compatibility with future devices,
should program M11, M10 = "0, 0"
Write Burst Mode
M9
Mode
Programmed Burst Length
Single Location Access
0
1
Operating Mode
M8 M7
0
— —
M6-M0
Defined
Mode
Standard Operation
All Other States Reserved
0
Burst Type
M3
Type
0
1
Sequential
Interleaved
Burst Length
M2 M1 M0
0
0
0
0
1
1
1
1
M3=0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3=1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Address Bus
Mode Register (Mx)
A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
(1)
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