參數(shù)資料
型號(hào)： IS42VS16400C1-12TLI
廠商： INTEGRATED SILICON SOLUTION INC
元件分類： DRAM
英文描述： 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述： 4M X 16 SYNCHRONOUS DRAM, 9 ns, PDSO54
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-54
文件頁(yè)數(shù)： 8/56頁(yè)
文件大?。?/td> 509K
代理商： IS42VS16400C1-12TLI
IS42VS16400C1
ISSI
8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
10/06/05
NOTE:
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table - CKE) and after t
XSR
has been met (if the
previous state was SELF REFRESH).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those
allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and t
RP
has been met.
Row Active: A row in the bank has been activated, and t
RCD
has been met. No data bursts/accesses and no register
accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or
allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to
the other bank are determined by its current state and CURRENT STATE BANK n truth tables.
Precharging: Starts with registration of a PRECHARGE command and ends when t
RP
is met. Once t
RP
is met, the bank
will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when t
RCD
is met. Once t
RCD
is met, the bank will
be in the row active state.
Read w/Auto
Precharge Enabled:
Starts with registration of a READ command with auto precharge enabled and ends when t
RP
has been met.
Once t
RP
is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled:
Starts with registration of a WRITE command with auto precharge enabled and ends when t
RP
has been met.
Once t
RP
is met, the bank will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be
applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when t
RC
is met. Once t
RC
is met, the
SDRAM will be in the all banks idle state.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when t
MRD
has been met. Once
t
MRD
is met, the SDRAM will be in the all banks idle state.
Precharging All:
Starts with registration of a PRECHARGE ALL command and ends when t
RP
is met. Once t
RP
is met, all
banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs
or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
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