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參數(shù)資料
| 型號： | IS43R16800A-6TL |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 8Meg x 16 128-MBIT DDR SDRAM |
| 中文描述： | 8M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | LEAD FREE, PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 23/47頁 |
| 文件大?。?/td> | 473K |
| 代理商： | IS43R16800A-6TL |
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev.
00
A
04/04/06
23
ISSI
IS43R16800A-6
Read/Write Operations
Bank active
A read or a write operation begins with the bank active command [ACT]. The bank active command determines a
bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after
the ACT is issued.
Read operation
The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read
command is issued. The burst length (BL) determines the length of a sequential output data by the read command
that can be set to 2, 4, or 8. The starting address of the burst read is defined by the column address, the bank select
address which are loaded via the A0 to A11 and BA0, BA1 pins in the cycle when the read command is issued. The
data output timing are characterized by CL and tAC. The read burst start CL
tCK + tAC (ns) after the clock rising
edge where the read command are latched. The DDR SDRAM output the data strobe through DQS simultaneously
with data. tRPRE prior to the first rising edge of the data strobe, the DQS are driven Low from VTT level. This low
period of DQS is referred as read preamble. The burst data are output coincidentally at both the rising and falling
edge of the data strobe. The DQ pins become High-Z in the next cycle after the burst read operation completed.
tRPST from the last falling edge of the data strobe, the DQS pins become High-Z. This low period of DQS is
referred as read postamble.
out0 out1
out0 out1 out2 out3
out0 out1 out2 out3
out4 out5 out6 out7
CK
/CK
Address
DQS
DQ
BL = 2
BL = 4
BL = 8
Command
CL = 2
BL: Burst length
t1
t0
t5
t4
t6
t7
t8
t9
tRCD
tRPRE
tRPST
ACT
NOP
NOP
NOP
READ
Row
Column
Read Operation (Burst Length)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS43R16800A1 | 8Meg x 16 128-MBIT DDR SDRAM |
| IS43R16800A1-5TL | 8Meg x 16 128-MBIT DDR SDRAM |
| IS43R32400A | 4Meg x 32 128-MBIT DDR SDRAM |
| IS43R32400A-5B | 4Meg x 32 128-MBIT DDR SDRAM |
| IS43R32400A-5BL | 4Meg x 32 128-MBIT DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS43R16800C-5TL | 功能描述:動態(tài)隨機存取存儲器 128M 8Mx16 200MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R16800C-5TL-TR | 功能描述:動態(tài)隨機存取存儲器 128M 8Mx16 200MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R16800CC-5TL | 功能描述:動態(tài)隨機存取存儲器 128M (8Mx16) 200MHz DDR 2.5v RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R16800CC-5TLI | 功能描述:動態(tài)隨機存取存儲器 128M (8Mx16) 200MHz DDR 2.5v RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R16800CC-5TLI-TR | 功能描述:動態(tài)隨機存取存儲器 128M (8Mx16) 200MHz DDR 2.5v RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
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