參數(shù)資料
型號(hào): IS43R16800A-6TL
廠(chǎng)商: INTEGRATED SILICON SOLUTION INC
元件分類(lèi): DRAM
英文描述: 8Meg x 16 128-MBIT DDR SDRAM
中文描述: 8M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝: LEAD FREE, PLASTIC, TSOP2-66
文件頁(yè)數(shù): 8/47頁(yè)
文件大?。?/td> 473K
代理商: IS43R16800A-6TL
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
Notes:
1. All AC parameters measuremed with the following test conditions.
2. This parameter defines the signal transition delay from the crossing point of CK and
CK
. The signal transition is defined to occur
when the signal level crosses VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal
transition is defined to occur when the signal level crosses VTT.
5. t
HZ
is defined as the data output transition delay from Low-Z to High-Z at the end of a read burst operation. The timing reference
is the crossing point of CK and
CK
. This parameter is not referred to a specific voltage level, but when the device output stops
driving.
6. t
LZ
is defined as the data output transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is referring
to a specific voltage level, but when the device output begins driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal
transition is defined to occur when the signal level crosses V
REF
.
8. The timing reference level is V
REF
.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. There is no specific reference voltage
to judge this transition.
10. t
CK
(max.) is determined by the locking range of the DLL. Beyond this lock range, the DLL operation is assured.
11. t
CK
= t
CK
(min) when these parameters are measured. Otherwise, absolute minimum values of these values are 10% of t
CK
.
12. VDD is assumed to be 2.5V ± 0.2V. V
DD
power supply variation per cycle expected to be less than 0.4V per 400 cycles.
13. t
DAL
= (t
WR
/t
CK
)+(t
RP
/t
CK
). For each of the add-ins, if not an integer already, round up to the nearest integer.
相關(guān)PDF資料
PDF描述
IS43R16800A1 8Meg x 16 128-MBIT DDR SDRAM
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IS43R32400A 4Meg x 32 128-MBIT DDR SDRAM
IS43R32400A-5B 4Meg x 32 128-MBIT DDR SDRAM
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