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參數資料
| 型號： | IS45LV44002B-50JLA1 |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE |
| 中文描述： | 4M X 4 EDO DRAM, 50 ns, PDSO24 |
| 封裝： | 0.300 INCH, LEAD FREE, PLASTIC, SOJ-24 |
| 文件頁數： | 3/20頁 |
| 文件大小： | 137K |
| 代理商： | IS45LV44002B-50JLA1 |
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
09/12/05
3
IS45LV44002B
ISSI
Functional Description
The IS45LV44002B is a CMOS DRAMs optimized for
high-speed bandwidth, low power applications. During
READ or WRITE cycles, each bit is uniquely addressed
through the 11 address bits. These are entered 11 bits
(A0-A10) at a time for the 2K refresh device. The row
address is latched by the Row Address Strobe (
RAS
). The
column address is latched by the Column Address Strobe
(
CAS
).
RAS
is used to latch the first nine bits and
CAS
is
used the latter ten bits.
Memory Cycle
A memory cycle is initiated by bringing
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE
,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time
specified by t
AR
. Data Out becomes valid only when t
RAC
,
t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access
time is dependent on the timing relationships between
these parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE
, whichever occurs last. The input data must be valid
at or before the falling edge of
CAS
or
WE
, whichever
occurs last.
Auto Refresh Cycle
To retain data, 2,048 refresh cycles are required in each
32 ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) with RAS at least once every 32 ms. Any
read, write, read-modify-write or RAS-only cycle re-
freshes the addressed row.
2. Using a
CAS
-before-
RAS
refresh cycle.
CAS
-before-
RAS
refresh is activated by the falling edge of
RAS
, while
holding
CAS
LOW. In
CAS
-before-
RAS
refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
CAS
-before-
RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the V
DD
supply, an initial pause of 200
μs is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
DD
or be held at a valid V
IH
to avoid current surges.
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| IS45S16100C1 | 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
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| IS45S16100C1-7BLA1 | 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS45S16100C1-7TA1 | 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS45S16100C1-7TLA | 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IS45S | 制造商:IDEC Corporation 功能描述:SENS.IND. 10-30VDC PNP NC |
| IS45S16100C1 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS45S16100C1-7BLA | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS45S16100C1-7BLA1 | 功能描述:動態(tài)隨機存取存儲器 64M (4Mx16) 143MHz Automotive Temp RoHS:否 制造商:ISSI 數據總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS45S16100C1-7BLA1-TR | 功能描述:動態(tài)隨機存取存儲器 16M (1Mx16) 143MHz Automotive Temp RoHS:否 制造商:ISSI 數據總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
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