參數(shù)資料
型號(hào): IS45S16800B-7TLA
廠(chǎng)商: INTEGRATED SILICON SOLUTION INC
元件分類(lèi): DRAM
英文描述: 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: LEAD FREE, PLASTIC, TSOP2-54
文件頁(yè)數(shù): 25/59頁(yè)
文件大?。?/td> 593K
代理商: IS45S16800B-7TLA
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
04/14/06
25
ISSI
IS45S81600B, IS45S16800B
DON'T CARE
UNDEFINED
CLK
COMMAND
DQ
READ
NOP
NOP
NOP
CAS Latency - 3
t
AC
t
OH
D
OUT
T0
T1
T2
T3
T4
t
LZ
CLK
COMMAND
DQ
READ
NOP
NOP
CAS Latency - 2
t
AC
t
OH
D
OUT
T0
T1
T2
T3
t
LZ
CAS LATENCY
CAS Latency
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or
three clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n + m. The DQs will start driving as a result of the clock edge
one cycle earlier (n + m 1), and provided that the relevant
access times are met, the data will be valid by clock edge
n + m. For example, assuming that the clock cycle time is
such that all relevant access times are met, if a READ
command is registered at T0 and the latency is programmed
to two clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in CAS Latency diagrams. The
Allowable Operating Frequency table indicates the operat-
ing frequencies at which each CAS latency setting can be
used.
Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
CAS Latency
Allowable Operating Frequency (MHz)
Speed
CAS Latency = 2
CAS Latency = 3
-7
100
143
Operating Mode
The normal operating mode is selected by setting M7 and M8
to zero; the other combinations of values for M7 and M8 are
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write
accesses are single-location (nonburst) accesses.
相關(guān)PDF資料
PDF描述
IS45S16800B-7TLA1 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
IS45S81600B 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
IS45S81600B-7TA 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
IS45S81600B-7TA1 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
IS45S81600B-7TLA 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
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