參數(shù)資料
型號(hào): IS45S81600B-7TA1
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
中文描述: 16M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: PLASTIC, TSOP2-54
文件頁(yè)數(shù): 23/59頁(yè)
文件大?。?/td> 593K
代理商: IS45S81600B-7TA1
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
04/14/06
23
ISSI
IS45S81600B, IS45S16800B
REGISTER DEFINITION
Mode Register
The mode register is used to define the specific mode of
operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, an
operating mode and a write burst mode, as shown in MODE
REGISTER DEFINITION.
The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
until it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst
(sequential or interleaved)
, M4- M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 are reserved for future use.
The mode register must be loaded when all banks are idle,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
MODE REGISTER DEFINITION
Latency Mode
M6 M5 M4
0
0
0
0
1
1
1
1
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1. To ensure compatibility with future devices,
should program BA1, BA0, A11, A10 = "0"
Write Burst Mode
M9
Mode
Programmed Burst Length
Single Location Access
0
1
Operating Mode
M
8
M7
0
— —
M6-M0
Defined
Mode
Standard Operation
All Other States Reserved
0
Burst Type
M3
Type
0
1
Sequential
Interleaved
Burst Length
M2 M1 M0
0
0
0
0
1
1
1
1
M3=0
1
2
4
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page
M3=1
1
2
4
8
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Address Bus
Mode Register (Mx)
(1)
BA1 BA A11 A10
A9
A
8
A7
A6
A5
A4
A3
A2
A1
A0
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