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參數(shù)資料
| 型號： | IS45S81600B-7TA |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM |
| 中文描述： | 16M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 5/59頁 |
| 文件大小： | 593K |
| 代理商： | IS45S81600B-7TA |
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Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
04/14/06
5
ISSI
IS45S81600B, IS45S16800B
PIN FUNCTIONS
Symbol
Type
Function (In Detail)
A0-A11
Input Pin
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (column address A0-A9
(x8), or A0-A8 (x16); with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a PRECHARGE command
to determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
BA0, BA1
Input Pin
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
CAS
Input Pin
CAS
, in conjunction with the
RAS
and
WE
, forms the device command. See the
"Command Truth Table" for details on device commands.
CKE
Input Pin
The CKE input determines whether the CLK input is enabled. The next rising edge of the
CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW,
the device will be in either power-down mode, clock suspend mode, or self refresh
mode.
CKE is an
asynchronous i
nput.
CLK
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
CS
Input Pin
The
CS
input determines whether command input is enabled within the device.
Command input is enabled when
CS
is LOW, and disabled with
CS
is HIGH. The device
remains in the previous state when
CS
is HIGH.
DQML,
DQMH
Input Pin
DQML and DQMH control the lower and upper bytes of the I/O buffers. In read
mode,DQML and DQMH control the output buffer. WhenDQML orDQMH is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the
HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds to
OE
in conventional DRAMs. In write mode,DQML and DQMH control the input buffer. When
DQML or DQMH is LOW, the corresponding buffer byte is enabled, and data can be
written to the device. WhenDQML or DQMH is HIGH, input data is masked and cannot
be written to the device. For IS45S16800B only.
DQM
Input Pin
For IS45S81600B only.
DQ
0
-DQ
7
or
DQ
0
-DQ
15
Input/Output
Data on the Data Bus is latched on DQ pins during Write commands, and buffered for
output after Read commands.
RAS
Input Pin
RAS
, in conjunction with
CAS
and
WE
, forms the device command. See the "Command
Truth Table" item for details on device commands.
WE
Input Pin
WE
, in conjunction with
RAS
and
CAS
, forms the device command. See the "Command
Truth Table" item for details on device commands.
V
DDQ
Power Supply Pin
V
DDQ
is the output buffer power supply.
V
DD
Power Supply Pin
V
DD
is the device internal power supply.
V
SSQ
Power Supply Pin
V
SSQ
is the output buffer ground.
V
SS
Power Supply Pin
V
SS
is the device internal ground.
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|---|---|
| IS45S81600B-7TA1 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM |
| IS45S81600B-7TLA | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS45S81600B-7TLA1 | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS45S81600E | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16M x 8, 8M x16 128Mb SYNCHRONOUS DRAM |
| IS45S81600E-6TLA1 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16M x 8, 8M x16 128Mb SYNCHRONOUS DRAM |
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