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| 型號(hào)： | IS61LPD102418A-200B3I |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| 中文描述： | 1M X 18 CACHE SRAM, 3.1 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165 |
| 文件頁(yè)數(shù)： | 8/29頁(yè) |
| 文件大?。?/td> | 219K |
| 代理商： | IS61LPD102418A-200B3I |
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8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/03/06
IS61VPD51236A, IS61VPD102418A, IS61LPD51236A ,IS61LPD102418A
ISSI
TRUTH TABLE
(1-8)
(3CE option)
OPERATION
ADDRESS
CE
CE2
CE2
ZZ
ADSP
ADSC
ADV
WRITE
OE
CLK
DQ
Deselect Cycle, Power-Down
None
H
X
X
L
X
L
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
X
L
L
L
X
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
H
X
L
L
X
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
X
L
L
H
L
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
H
X
L
H
L
X
X
X
L-H
High-Z
Snooze Mode, Power-Down
None
X
X
X
H
X
X
X
X
X
X
High-Z
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
H
L-H
High-Z
Write Cycle, Begin Burst
External
L
L
H
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
High-Z
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
High-Z
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For
WRITE
, L means one or more byte write enable signals (
BWa
,
BWb
,
BWc
or
BWd
) and
BWE
are LOW or
GW
is LOW.
WRITE
= H for all
BWx
,
BWE
,
GW
HIGH.
3.
BWa
enables WRITEs to DQa’s and DQPa.
BWb
enables WRITEs to DQb’s and DQPb.
BWc
enables WRITEs to DQc’s and
DQPc.
BWd
enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and
DQPd are only available on the x36 version.
4. All inputs except
OE
and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation,
OE
must be HIGH before the input data setup time and held HIGH during the
input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8.
ADSP
LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
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| IS61LPD102418A-200TQ | 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD102418A-200TQI | 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD102418A-250B3 | 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD102418A-250B3I | 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD102418A-250TQ | 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61LPD102418A-200B3I-TR | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18Mb,Pipeline,Sync,1Mb x 18,200MHz,3.3V or 2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61LPD102418A-200TQ | 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD102418A-200TQI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18Mb 1Mbx18 200MHz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 3.3v RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61LPD102418A-200TQI-TR | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18Mb 1Mbx18 200MHz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 3.3v RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61LPD102418A-250B3 | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18Mb,Pipeline,Sync,1Mb x 18,250MHz,3.3V or 2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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