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參數(shù)資料
| 型號： | IS61LPD51218A-250TQ |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| 中文描述： | 512K X 18 CACHE SRAM, 2.6 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 216K |
| 代理商： | IS61LPD51218A-250TQ |
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/09/05
19
IS61VPD25636A, IS61VPD51218A, IS61LPD25636A, IS61LPD51218A
ISSI
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
The IS61LPD/VPD25636A and IS61LPD/VPD51218A have
a serial boundary scan Test Access Port (TAP) in the PBGA
package only. (The TQFP package not available.) This port
operates in accordance with
IEEE
Standard 1149.1-1900,
but does not include all functions required for full 1149.1
compliance. These functions from the
IEEE specification
are
excluded because they place added delay in the critical
speed path of the SRAM. The TAP controller operates in a
manner that does not conflict with the performance of other
devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 2.5V I/O logic levels.
DISABLING THE JTAG FEATURE
The SRAM can operate without using the JTAG feature. To
disable the TAP controller, TCK must be tied LOW (Vss) to
prevent clocking of the device. TDI and TMS are internally
pulled up and may be disconnected. They may alternately
be connected to V
DD
through a pull-up resistor. TDO should
be left disconnected. On power-up, the device will start in a
reset state which will not interfere with the device operation.
TEST ACCESS PORT (TAP) - TEST CLOCK
The test clock is only used with the TAP controller. All
inputs are captured on the rising edge of TCK and outputs
are driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The
pin is internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information to the
registers and can be connected to the input of any
register. The register between TDI and TDO is chosen by
the instruction loaded into the TAP instruction register.
For information on instruction register loading, see the
TAP Controller State Diagram. TDI is internally pulled up
and can be disconnected if the TAP is unused in an
application. TDI is connected to the Most Significant Bit
(MSB) on any register.
31 30 29
. . .
Identification Register
2
1
0
2
1
0
0
x
. . . . .
Boundary Scan
Register*
2
1
0
Bypass Register
Instruction Register
TAP CONTROLLER
Selection Circuitry
Selection Circuitry
TDO
TDI
TCK
TMS
TAP CONTROLLER BLOCK DIAGRAM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS61LPD51218A-250TQI | 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPS12832A | 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS12832A-200B2 | 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS12836A-200TQLI | 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
| IS61LPS12836A-250B2 | 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61LPD51218A-250TQI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51218T/D | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE-CYCLE DESELECT STATIC RAM |
| IS61LPD51236A | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM |
| IS61LPD51236A-200B3 | 功能描述:靜態(tài)隨機存取存儲器 18Mb 512Kx36 200MHz Sync 靜態(tài)隨機存取存儲器 3.3v RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61LPD51236A-200B3I | 功能描述:靜態(tài)隨機存取存儲器 18Mb,Pipeline,Sync,512K x 36,200MHz,3.3V or 2.5V I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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