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參數(shù)資料
| 型號： | IS61LV25616L-15KI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY |
| 中文描述： | 256K X 16 STANDARD SRAM, 15 ns, PDSO44 |
| 封裝： | 0.400 INCH, SOJ-44 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 74K |
| 代理商： | IS61LV25616L-15KI |
10
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
06/28/02
IS61LV25616L
ISSI
AC WAVEFORMS
WRITE CYCLE NO. 4
(
LB
,
UB
Controlled, Back-to-Back Write)
(1,3)
DATA UNDEFINED
t
WC
ADDRESS 1
ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
LOW
WORD 2
UB_CEWR4.eps
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
t
PBW
DATA
IN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
Notes:
1. The internal Write time is defined by the overlap of
CE
= LOW,
UB
and/or
LB
= LOW, and
WE
= LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The
t
SA
,
t
HA
,
t
SD
, and
t
HD
timing is referenced to the
rising or falling edge of the signal that terminates the Write.
2. Tested with
OE
HIGH for a minimum of 4 ns before
WE
= LOW to place the I/O in a HIGH-Z state.
3.
WE
may be held LOW across many address cycles and the
LB
,
pins can be used to control the Write function.
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| IS61LV25616L-15T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY |
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| IS61LV256-20JI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:32K X 8 LOW VOLTAGE CMOS STATIC RAM |
| IS61LV256-20N | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:32K x 8 LOW VOLTAGE CMOS STATIC RAM |
| IS61LV256-20NI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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