參數(shù)資料
型號: IS61LV6424
廠商: Integrated Silicon Solution, Inc.
英文描述: 64K x 24 High-Speed CMOS Static RAM(3.3V,64K x 24 高速CMOS靜態(tài)RAM)
中文描述: 64K的× 24高速CMOS靜態(tài)RAM(3.3伏,64K的× 24高速的CMOS靜態(tài)RAM)的
文件頁數(shù): 1/10頁
文件大?。?/td> 103K
代理商: IS61LV6424
FEATURES
High-speed access time: 9, 10, 12, 15 ns
CMOS low power operation
594 mW (max.) operating @ 9 ns
36 mW (max.) CMOS standby
TTL compatible interface levels
Single 3.3V power supply
Fully static operation: no clock or refresh
required
Three state outputs
Available in 100-pin TQFP
Industrial temperature available
DESCRIPTION
The
ISSI
IS61LV6424 is a high-speed, static RAM organized
as 65,536 words by 24 bits. It is fabricated using
ISSI
's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields ac-
cess times as fast as 9 ns with low power consumption.
When
CE1
is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE1
, CE2, and
OE
. The active LOW
Write Enable (
WE
) controls both writing and reading of the
memory.
The IS61LV6424 is packaged in the JEDEC standard
100-pin TQFP
FUNCTIONAL BLOCK DIAGRAM
DECEMBER 2000
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. Copyright 2000, Integrated Silicon Solution, Inc.
IS61LV6424
64K x 24 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
ISSI
A0-A14
CE1
CE2
OE
WE
64K x 24
MEMORY ARRAY
ROW
DECODER
COLUMN
DECODER
I/O DATA
CIRCUIT
I/O0-I/O23
CONTROL
CIRCUIT
GND
V
CC
MULTIPLEX
ADDRESS
CONTROL
X/
Y
V/
S
A15
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
1
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