參數(shù)資料
型號: IS62LV5128LL-70BI
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 512K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM
中文描述: 512K X 8 STANDARD SRAM, 70 ns, PBGA36
封裝: 8 X 10 MM, MINI, BGA-36
文件頁數(shù): 7/10頁
文件大?。?/td> 61K
代理商: IS62LV5128LL-70BI
Integrated Silicon Solution, Inc.
1-800-379-4774
Rev. D
05/04/01
7
IS62LV5128LL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range, Standard and Low Power)
-70
-85
Symbol
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
(4)
t
SD
t
HD
t
HZWE
(2)
t
LZWE
(2)
Notes:
1.
Test conditions assume signal transition times of 5 ns or ess, timing reference evels of 1.5V, nput pulse evels of 0.4V to 2.2V and output oading specified n Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.
The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the
Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
4. Tested with
OE
HIGH.
Parameter
Min.
Max.
Min.
Max.
Unit
Write Cycle Time
70
85
ns
CE
to Write End
65
70
ns
Address Setup Time to Write End
65
70
ns
Address Hold from Write End
0
0
ns
Address Setup Time
0
0
ns
WE
Pulse Width
60
60
ns
Data Setup to Write End
30
35
ns
Data Hold from Write End
0
0
ns
WE
LOW to High-Z Output
33
35
ns
WE
HIGH to Low-Z Output
5
5
ns
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCE
t
AW
t
HA
t
PWE
(4)
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CE
WE
DOUT
DIN
AC WAVEFORMS
WRITE CYCLE NO. 1
(
CE
Controlled,
OE
= HIGH or LOW)
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