參數(shù)資料
型號: IS62WV12816BLL-55TLI
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 128K x 16 LOW VOLTAGE ULTRA LOW POWER CMOS STATIC RAM
中文描述: 128K X 16 STANDARD SRAM, 55 ns, PDSO44
封裝: 0.400 INCH, LEAD FREE, TSOP2-44
文件頁數(shù): 9/17頁
文件大?。?/td> 112K
代理商: IS62WV12816BLL-55TLI
IS62WV12816ALL, IS62WV12816BLL
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. E
06/08/05
9
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
45ns
55 ns
70 ns
Symbol
t
WC
t
SCS1/
t
SCS2
CS1/
CS2 to Write End
t
AW
Address Setup Time to Write End
t
HA
Address Hold from Write End
t
SA
Address Setup Time
t
PWB
LB
,
UB
Valid to End of Write
t
PWE
WE
Pulse Width
t
SD
Data Setup to Write End
t
HD
Data Hold from Write End
t
HZWE
(3)
WE
LOW to High-Z Output
t
LZWE
(3)
WE
HIGH to Low-Z Output
Parameter
Write Cycle Time
Min.
45
35
35
0
0
35
35
20
0
5
Max.
20
Min.
55
45
45
0
0
45
40
25
0
5
Max.
20
Min.
70
60
60
0
0
60
50
30
0
5
Max.
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V
and output loading specified in Figure 1.
2.
The internal write time is defined by the overlap of
CS1
LOW, CS2 HIGH and
UB
or
LB
, and
WE
LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
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IS62WV12816ALL-70B2I Circular Connector; No. of Contacts:6; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No
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