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參數(shù)資料
| 型號(hào)： | IS64LV6416L-10TA1 |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 64K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY |
| 中文描述： | 64K X 16 STANDARD SRAM, 10 ns, PDSO44 |
| 封裝： | PLASTIC, TSOP2-44 |
| 文件頁(yè)數(shù)： | 5/14頁(yè) |
| 文件大?。?/td> | 94K |
| 代理商： | IS64LV6416L-10TA1 |
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IS64LV6416L
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
05/02/03
5
1
2
3
4
5
6
7
8
9
10
11
12
ISSI
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-10 ns
-12 ns
Min.
Symbol
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
HZOE
(2)
t
LZOE
(2)
t
HZCE
(2
t
LZCE
(2)
t
BA
t
HZB
t
LZB
Parameter
Min.
Max.
Max.
Unit
Read Cycle Time
10
—
12
—
ns
Address Access Time
—
10
—
12
ns
Output Hold Time
3
—
3
—
ns
CE
Access Time
—
10
—
12
ns
OE
Access Time
—
5
—
6
ns
OE
to High-Z Output
—
5
—
6
ns
OE
to Low-Z Output
0
—
0
—
ns
CE
to High-Z Output
0
5
0
6
ns
CE
to Low-Z Output
3
—
3
—
ns
LB
,
UB
Access Time
—
6
—
6
ns
LB
,
UB
to High-Z Output
0
5
0
6
ns
LB
,
UB
to Low-Z Output
0
—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1a and 1b
AC TEST LOADS
Figure 1a. Figure 1b.
319
30 pF
Including
jig and
scope
353
OUTPUT
3.3V
319
5 pF
Including
jig and
scope
353
OUTPUT
3.3V
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