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參數(shù)資料
| 型號： | IS64LV6416L-12BA2 |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 64K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY |
| 中文描述： | 64K X 16 STANDARD SRAM, 12 ns, PBGA48 |
| 封裝： | 6 X 8 MM, MINI, BGA-48 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 94K |
| 代理商： | IS64LV6416L-12BA2 |
IS64LV6416L
10
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
05/02/03
ISSI
DATA UNDEFINED
t
WC
ADDRESS 1
ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
LOW
WORD 2
UB_CEWR4.eps
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB
,
LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
t
PBW
DATA
IN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
WRITE CYCLE NO. 4
(
LB
,
UB
Controlled, Back-to-Back Write)
(1,3)
Notes:
1. The internal Write time is defined by the overlap of
CE
= LOW,
UB
and/or
LB
= LOW, and
WE
= LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The
t
SA
,
t
HA
,
t
SD
, and
t
HD
timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with
OE
HIGH for a minimum of 4 ns before
WE
= LOW to place the I/O in a HIGH-Z state.
3.
WE
may be held LOW across many address cycles and the
LB
,
UB
pins can be used to control the Write function.
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相關代理商/技術參數(shù) |
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|---|---|
| IS64LV6416L-12BA3 | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS64LV6416L-12BA3-TR | 制造商:Integrated Silicon Solution Inc 功能描述: |
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| IS64LV6416L-12TA2 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:64K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY |
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