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參數(shù)資料
| 型號(hào)： | IS65C256AL-45ULA3 |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 32K x 8 LOW POWER CMOS STATIC RAM |
| 中文描述： | 32K X 8 STANDARD SRAM, 45 ns, PDSO28 |
| 封裝： | 0.330 INCH, LEAD FREE, PLASTIC, SOP-28 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 101K |
| 代理商： | IS65C256AL-45ULA3 |
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
7
ISSI
IS65C256AL
IS62C256AL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-25 ns
Min.
-45 ns
Min. Max.
Symbol
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
1,
t
PWE
2
(4)
t
SD
t
HD
Parameter
Max.
Unit
Write Cycle Time
25
—
45
—
ns
CE
to Write End
15
—
35
—
ns
Address Setup Time to Write End
15
—
25
—
ns
Address Hold from Write End
0
—
0
—
ns
Address Setup Time
0
—
0
—
ns
WE
Pulse Width
15
—
25
—
ns
Data Setup to Write End
12
—
20
—
ns
Data Hold from Write End
0
—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
4. Tested with
OE
HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1
(
CE
Controlled,
OE
is HIGH or LOW)
(1 )
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCS
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
CS_WR1.eps
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| IS65C51216AL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
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| IS65C51216AL-55MLA3 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
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