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參數(shù)資料
| 型號(hào)： | IS65C256AL-45ULA3 |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 32K x 8 LOW POWER CMOS STATIC RAM |
| 中文描述： | 32K X 8 STANDARD SRAM, 45 ns, PDSO28 |
| 封裝： | 0.330 INCH, LEAD FREE, PLASTIC, SOP-28 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大小： | 101K |
| 代理商： | IS65C256AL-45ULA3 |
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
ISSI
IS65C256AL
IS62C256AL
AC WAVEFORMS
WRITE CYCLE NO. 2
(
OE
is HIGH During Write Cycle)
(1,2)
WRITE CYCLE NO. 3
(
OE
is LOW During Write Cycle)
(1)
Notes:
1. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
2. I/O will assume the High-Z state if
OE
= V
IH
.
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CS_WR2.eps
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CS_WR3.eps
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