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參數(shù)資料
| 型號(hào)： | IS65LV256AL-45ULA3 |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 32K x 8 LOW VOLTAGE CMOS STATIC RAM |
| 中文描述： | 32K X 8 STANDARD SRAM, 45 ns, PDSO28 |
| 封裝： | 0.330 MM, LEAD FREE, PLASTIC, SOP-28 |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大?。?/td> | 113K |
| 代理商： | IS65LV256AL-45ULA3 |
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IS65LV256AL
IS62LV256AL
ISSI
8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
03/17/06
Notes:
1. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
≥
V
IH
.
HIGH-Z
DATA UNDEFINED
DATA-IN VALID
t
WC
t
SCE
t
SA
t
HA
t
PWE
t
AW
t
HZWE
t
SD
t
HD
t
LZWE
ADDRESS
D
IN
CE
WE
D
OUT
WRITE CYCLE NO. 2 (
CE
Controlled)
(1,2)
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