參數(shù)資料
型號(hào)： IS75V16F128GS32
廠商： Integrated Silicon Solution, Inc.
英文描述： 3.0 Volt Multi-Chip Package (MCP) 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM
中文描述： 3.0伏多芯片封裝（MCP）128兆位同步運(yùn)行閃存和32兆位偽靜態(tài)RAM
文件頁數(shù)： 39/52頁
文件大?。?/td> 264K
代理商： IS75V16F128GS32
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00D
03/24/03
39
IS75V16F128GS32
ISSI
PSRAM WRITE OPERATIONS
Value
Parameter
Symbol
Min.
Max.
Unit
Write Cycle Time
(1)
t
WC
70
—
ns
Address Setup Time
(2)
t
AS
0
—
ns
Address Hold Time
(2)
t
AH
35
—
ns
CE
1r Write Setup Time
t
CS
0
1000
ns
CE
1r Write Hold Time
t
CH
0
1000
ns
WE
Setup Time
t
WS
0
—
ns
WE
Hold Time
t
WH
0
—
ns
LB
adnd
UB
Setup Time
t
BS
-5
—
ns
LB
adnd
UB
Hold Time
t
BH
-5
—
ns
OE
Setup Time
(3)
t
OES
0
1000
ns
OE
Hold Time
(3,4)
t
OEH
25
1000
ns
OE
Hold Time
(5)
t
OEH
(
ABS
)
12
—
ns
OE
High to
CE
1r Low Setup Time
(6)
t
OHCL
-5
—
ns
OE
High to Address Hold Time
(7)
t
OHAH
-5
—
ns
CE
1r Write Pulse Width
(1,8)
t
CW
45
—
ns
WE
Write Pulse Width
(1,8)
t
WP
45
—
ns
CE
1r Write Recovery Time
(1,9)
t
WRC
10
—
ns
WE
Write Recovery Time
(1,3,9)
t
WR
10
1000
ns
Data Setup Time
t
DS
15
—
ns
Data Hold Time
t
DH
0
—
ns
CE
1r High Pulse Width
(9)
Notes:
1. Minimum value must be equal or greater than the sum of actual t
CW
(or t
WP
) and t
WRC
(or t
WR
).
2. New write address is valid from either
CE
1r or
WE
that is brought to High.
3. Maximum value is applicable if
CE
1r is kept at Low and both
WE
and
OE
are kept at High.
4. The t
OEH
is specified from end of t
WC
(Min), and is a reference value when access time is determined by t
OE
.
If actual value is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual
value from specified minimum value.
5. The t
OEH
[
ABS
] is the absolute minimum value if write cycle is terminated by
WE
and
CE
1r stay Low.
6. t
OHCL
(Min) must be satisfied if read operation is not performed prior to write operation.
In case
OE
is disabled after t
OHCL
(Min),
WE
Low must be asserted after t
RC
(Min) from
CE
1r Low.
In other words, read operation is initiated if t
OHCL
(Min) is not satisfied.
7. Applicable if
CE
1r stays Low after read operation.
8. t
CW
and t
WP
are applicable if write operation is initiated by
CE
1r and
WE
, respectively.
9. t
WRC
and t
WR
are applicable if write operation is terminated by
CE
1r and
WE
, respectively.
The t
WR
(Min) can be ignored if
CE
1r is brought to High together or after
WE
is brought to High.
In such a case, the t
CP
(Min) must be satisfied.
t
CP
12
—
ns
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IS75V16F128GS32-7065BI 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:3.0 Volt Multi-Chip Package (MCP) 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM
IS75V16F64GS16-7080DI 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:64 Mbit FLASH MEMORY AND 16 Mbit PSEUDO SRAM STACKED MULTI-CHIP PACKAGE (MCP)
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