參數(shù)資料
型號(hào)： IS75V16F128GS32-7065BI
廠商： INTEGRATED SILICON SOLUTION INC
元件分類： 存儲(chǔ)器
英文描述： 3.0 Volt Multi-Chip Package (MCP) 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA107
封裝： 9 X 10 MM, 0.80 MM PITCH, FBGA-107
文件頁數(shù)： 1/52頁
文件大?。?/td> 264K
代理商： IS75V16F128GS32-7065BI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00D
03/24/03
1
IS75V16F128GS32
ISSI
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products. FlexBankTM is a trademark
of Fujitsu Limited, Japan. Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc
3.0 Volt Multi-Chip Package (MCP)
— 128 Mbit Simultaneous Operation Flash
Memory and 32 Mbit Pseudo Static RAM
PRELIMINARY INFORMATION
MARCH 2003
MCP FEATURES
Power supply voltage 2.7V to 3.3V
High performance:
Flash: 70ns maximum access time
PSRAM: 65ns maximum access time
Package: 107-ball BGA
Operating Temperature: -30C to +85C
FLASH FEATURES
Power Dissipation:
Read Current at 1 Mhz: 4 mA maximum
Read Current at 5 Mhz:18 mA maximum
Sleep Mode: 5
μ
A maximum
User Configurable Banks
Flash 1 (64 Mbit)
Bank A1: 8Mbit (8KB x 8 and 64KB x 15)
Bank B1: 24Mbit (64KB x 48)
Bank C1: 24Mbit (64KB x 48)
Bank D1: 8Mbit (8KB x 8 and 64KB x 15)
Flash 2 (64 Mbit)
Bank A2: 8Mbit (8KB x 8 and 64KB x 15)
Bank B2: 24Mbit (64KB x 48)
Bank C2: 24Mbit (64KB x 48)
Bank D2: 8Mbit (8KB x 8 and 64KB x 15)
User chooses two virtual banks from a
combination of four physical banks
Simultaneous R/W Operations (dual virtual bank):
Zero latency between read and write operations; Data
can be programmed or erased in one bank while data
is simultaneously being read from the other bank
Low-Power Mode:
A period of no activity causes flash to enter a
low-power state
Erase Suspend/Resume:
Suspends of erase activity to allow a read in the
same bank
Sector Erase Architecture:
16 sectors of 4K words each and 126 sectors of 32K words
each in Word mode.
Any combination of sectors, or
the entire flash can be simultaneously erased
Erase Algorithms:
Automatically preprograms/erases the flash memory
entirely, or by sector
Program Algorithms:
Automatically writes and verifies data at specified
address
Hidden ROM Region:
256 byte with a Factory-serialized secure electronic
serial number (ESN), which is accessible through a
command sequence
Data Polling and Toggle Bit:
Detects the completion of the program or erase cycle
Ready-Busy Outputs (RY/
BY
)
Detection of program or erase cycle completion for
each flash chip
Over 100,000 write/erase cycles
Low supply voltage (Vccf
≤
2.5V) inhibits writes
WP
/ACC input pin:
If V
IL
, allows partial protection of boot sectors
If V
IH
, allows removal of boot sector protection
If Vacc, program time is improved
PSRAM FEATURES (32 Mb density)
Power Dissipation:
Operating: 25 mA maximum
Standby: 110 μA maximum
Chip Selects:
CE1
r, CE2r
Power down feature using CE2r
Sleep Mode: 10 μA maximum
Nap: 65 μA maximum
8 mbit Partial: 80 μA maximum
Data retention supply voltage: 2.1 V to 3.3V
Byte data control:
LB
(DQ0–DQ7),
UB
(DQ8–DQ15)
相關(guān)PDF資料
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IS75V16F64GS16-7080DI 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:64 Mbit FLASH MEMORY AND 16 Mbit PSEUDO SRAM STACKED MULTI-CHIP PACKAGE (MCP)
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