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參數(shù)資料
| 型號： | IS9108-11CS14LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | 100.23 MHz, OTHER CLOCK GENERATOR, PDSO14 |
| 封裝： | SOIC-14 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 1089K |
| 代理商： | IS9108-11CS14LF |
Pin Configuration
Pin Descriptions for AV9108-03, AV9108-05 and AV9108-10
PIN NUMBER
PIN
NAME
TYPE
DESCRIPTION
-05/-10/-13
-03
1
14
FS0
Input
Frequency Select 0 for CLK1 (-03 has pull-up).
5
1
FS1
Input
Frequency Select 1 for CLK1 (-03 has pull-up).
2
FS2
Input
Frequency Select 2 for CLK1 (-03 has pull-up).
3
FS3
Input
Frequency Select 3 for CLK1 (-03 has pull-up).
4
AGND
-
Analog GROUND.
2
5
GMD
-
Digital GROUND.
6
PD
Input
POWER-DOWN. Shuts off chip when low. Internal pull-up.
3
7
X1/ICLK
Input
CRYSTAL OUTPUT or INPUT CLOCK frequency. Typically 14.318 MHz
system clock.
4
8
X2
Output
CRYSTAL OUTPUT (No Connect when clock used.).
9
OE(REFCLK)
Input
OUTPUT ENABLE. Tristates REFCLK when low. Pull-up.
10
OE(CLK1)
Input
OUTPUT ENABLE. Tristates CLK1 when low. Pull-up.
6
11
CLK1
Output
CLOCK1 Output (see decoding tables).
7
12
VDD
-
Digital power supply (+3V DC).
8
13
REFCLK
Output
REFERENCE CLOCK output. Produces a buffered version of the input clock or
crystal frequency (typically 14.318 MHz).
FS0
1
8
REFCLK
GND
2
7
VDD
X1/ICLK
3
6
CLK1
X2
4
5
FS1
AV9108-05/-10
8-Pin DIP, SOIC
FS1
1
14
FS0
FS2
2
13
REFCLK
FS3
3
12
VDD
AGND
4
11
CLK1
GND
5
10
OE (CLK1)
PD
6
9
OE (REFCLK)
X1/ICLK
7
8
X2
AV9108-03/-11
14-Pin DIP, SOIC
AV9108
2
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