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參數(shù)資料
| 型號： | ISD-300A1 |
| 英文描述： | Universal Serial Bus |
| 中文描述： | 通用串行總線 |
| 文件頁數(shù)： | 17/67頁 |
| 文件大?。?/td> | 580K |
| 代理商： | ISD-300A1 |
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ISD-300A1
12
October 19, 2001
Address
Field Name
Description
On-board
ROM Defaults
0xB
ATA Data Setup
Drive Power Valid
Polarity
Override PIO Timing
Drive Power Valid
Enable
ATA Read Kludge
I_MODE
Bits (7:5)
Setup time is only incurred on the first data cycle of a burst. Standard values
for ATA compliant devices and a 30.0 MHz system clock are (in binary):
Note: These values are only valid when the Override PIO Timing
configuration bit is set.
mode 0 010 (2+1)*33.33 = 133 ns
mode 1 001 (1+1)*33.33 = 66 ns
mode 2 001 (1+1)*33.33 = 66 ns
mode 3 001 (1+1)*33.33 = 66 ns
mode 4 000 (0+1)*33.33 = 33 ns
Bit (4)
Controls the polarity of DRV_PWR_VALID pin
0
Active low (“connector ground” indication)
1
Active high (power indication from device)
Bit (3)
This field is used in conjunction with ATA Data Setup, ATA Data Assertion,
ATA Data Recover, and PIO Mode Selection fields.
0
Use timing information acquired from the Drive
1
Override device timing information with configuration values
Bit (2)
Enable for the DRV_PWR_VALID pin. Drive Power Valid should only be
enabled in cable applications where the ISD-300A1 is VBUS powered.
0
pin disabled (most systems)
1
pin enabled
Bit(1)
PIO data read 3-state control. Enabling this will 3-state (hi-Z) the ATA data
bus during PIO read operations while addressing the data register. In most
applications this bit is set to ‘0’. This functionality is provided as a solution
for devices that erroneously drive the ATA data bus continuously during PIO
data register reads.
0
Normal operation as per ATA/ATAPI interface specification.
1
3-state (hi-Z) DD[15:0] during PIO data register reads.
Bit (0) – read only
This bit reflects the current state of the I_MODE input pin.
0x40
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