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參數(shù)資料
| 型號(hào)： | ISL12027IV27Z-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CALENDAR EEPROM 8-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年，監(jiān)控器，監(jiān)視計(jì)時(shí)器 |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ISL12027IV27Z-TDKR |
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22
FN8232.8
August 12, 2010
Application Section
Crystal Oscillator and Temperature Compensation
Intersil has now integrated the oscillator compensation
circuity on-chip, to eliminate the need for external
components and adjust for crystal drift over-temperature and
enable very high accuracy time keeping (<5ppm drift).
The Intersil RTC family uses an oscillator circuit with on-chip
crystal compensation network, including adjustable
load-capacitance. The only external component required is
the crystal. The compensation network is optimized for
operation with certain crystal parameters which are common
in many of the surface mount or tuning-fork crystals available
today. Table 8 summarizes these parameters.
Table 9 contains some crystal manufacturers and part numbers
that meet the requirements for the Intersil RTC products.
The turnover temperature in Table 8 describes the
temperature where the apex of the of the drift vs temperature
curve occurs. This curve is parabolic with the drift increasing
as (T - T0)2. For an Epson MC-405 device, for example, the
turnover temperature is typically +25°C, and a peak drift of
>110ppm occurs at the temperature extremes of -40°C and
+85°C. It is possible to address this variable drift by adjusting
the load capacitance of the crystal, which will result in
predictable change to the crystal frequency. The Intersil RTC
family allows this adjustment over temperature since the
devices include on-chip load capacitor trimming. This control
is handled by the Analog Trimming Register, or ATR, which
has 6-bits of control. The load capacitance range covered by
the ATR circuit is approximately 3.25pF to 18.75pF, in
0.25pF increments. Note that actual capacitance would also
include about 2pF of package related capacitance. In-circuit
tests with commercially available crystals demonstrate that
this range of capacitance allows frequency control from
+116ppm to -37ppm, using a 12.5pF load crystal.
In addition to the analog compensation afforded by the
adjustable load capacitance, a digital compensation feature
is available for the Intersil RTC family. There are 3-bits
known as the Digital Trimming Register or DTR, and they
operate by adding or skipping pulses in the clock signal. The
range provided is ±30ppm in increments of 10ppm. The
default setting is 0ppm. The DTR control can be used for
coarse adjustments of frequency drift over-temperature or
for crystal initial accuracy correction.
A final application for the ATR control is in-circuit calibration for
high accuracy applications, along with a temperature sensor
chip. Once the RTC circuit is powered up with battery backup,
and frequency drift is measured. The ATR control is then
adjusted to a setting, which minimizes drift. Once adjusted at a
particular temperature, it is possible to adjust at other discrete
temperatures for minimal overall drift, and store the resulting
settings in the EEPROM. Extremely low overall temperature
drift is possible with this method. The Intersil evaluation board
contains the circuitry necessary to implement this control.
Layout Considerations
The crystal input at X1 has a very high impedance and will pick
up high frequency signals from other circuits on the board.
Since the X2 pin is tied to the other side of the crystal, it is also
a sensitive node. These signals can couple into the oscillator
0
SLAVE
ADDRESS
WORD
ADDRESS 1
A
C
K
A
C
K
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
DATA
A
C
K
1
S
T
A
R
T
SDA BUS
SIGNALS FROM
THE SLAVE
SIGNALS FROM
THE MASTER
A
C
K
WORD
ADDRESS 0
1
11
00 0 0 0 0 0
FIGURE 25. RANDOM ADDRESS READ SEQUENCE
DATA
(2)
S
T
O
P
SLAVE
ADDRESS
DATA
(n)
A
C
K
A
C
K
SDA BUS
SIGNALS FROM
THE SLAVE
SIGNALS
FROM
THE MASTER
1
DATA
(n - 1)
A
C
K
A
C
K
(n IS ANY INTEGER GREATER THAN 1)
DATA
(1)
FIGURE 26. SEQUENTIAL READ SEQUENCE
ISL12027, ISL12027A
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