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參數(shù)資料
| 型號： | ISL12027IV27Z-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CALENDAR EEPROM 8-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年，監(jiān)控器，監(jiān)視計(jì)時(shí)器 |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ISL12027IV27Z-TDKR |
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13
FN8232.8
August 12, 2010
Alarm Registers (Non-Volatile)
Alarm0 and Alarm1
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match. See “Device Operation” on page 14
and “Application Section” on page 22 for more information.
Control Registers (Non-Volatile)
The Control Bits and Registers described in the following
section are non-volatile.
BL Register
BP2, BP1, BP0 - Block Protect Bits
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected
block of memory is ignored. The block protect bits will
prevent write operations to one of eight segments of the
array. The partitions are described in Table 3.
Oscillator Compensation Registers
There are two trimming options.
ATR. Analog Trimming Register
DTR. Digital Trimming Register
These registers are non-volatile. The combination of analog
and digital trimming can give up to -64 to +110ppm of total
adjustment.
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,
ATR0: Analog Trimming Register
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34ppm
to +80ppm to the nominal frequency compensation.
The effective on-chip series load capacitance, CLOAD,
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). CLOAD is changed via two digitally
controlled capacitors, CX1 and CX2, connected from the X1
and X2 pins to ground (see Figure 12). The value of CX1 and
CX2 is given Equation 1:
The effective series load capacitance is the combination of
CX1 and CX2:
For example, CLOAD(ATR = 00000) = 12.5pF,
CLOAD(ATR = 100000) = 4.5pF, and
CLOAD(ATR = 011111) = 20.25pF. The entire range for the
series combination of load capacitance goes from 4.5pF to
20.25pF in 0.25pF steps. Note that these are typical values.
DTR Register - DTR2, DTR1, DTR0: Digital
Trimming Register
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the
number of counts per second and average the ppm error to
achieve better accuracy.
DTR2 is a sign bit. DTR2 = 0 means frequency
compensation is >0. DTR2 = 1 means frequency
compensation is <0.
DTR1 and DTR0 are scale bits. DTR1 gives 10ppm
adjustment and DTR0 gives 20ppm adjustment.
A range from -30ppm to +30ppm can be represented by
using the three DTR bits.
TABLE 3.
BP2
BP1
BP0
PROTECTED ADDRESSES
ISL12027
ARRAY LOCK
0
None (Default)
None
0
1
180h – 1FFh
Upper 1/4
0
1
0
100h – 1FFh
Upper 1/2
0
1
000h – 1FFh
Full Array
10
0
000h – 03Fh
First 4 Pages
10
1
000h – 07Fh
First 8 Pages
1
0
000h – 0FFh
First 16 Pages
1
000h – 1FFh
Full Array
FIGURE 12. DIAGRAM OF ATR
CX1
X1
X2
CRYSTAL
OSCILLATOR
CX2
CX
16 b5
8b4 4 b3 2b2 1 b1 0.5b0 9
+
+
+
+
+
+
()pF
=
(EQ. 1)
CLOAD
1
CX1
-----------
1
CX2
-----------
+
-----------------------------------
=
CLOAD
16 b5
8 b4 4 b3 2 b2 1 b1 0.5 b0 9
+
+
+
+
+
+
2
-----------------------------------------------------------------------------------------------------------------------------
pF
=
(EQ. 2)
ISL12027, ISL12027A
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