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參數(shù)資料
| 型號(hào)： | ISL12082IB8Z-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 11/26頁 |
| 文件大小： | 0K |
| 描述： | IC RTC I2C LO-POWER 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年，監(jiān)視計(jì)時(shí)器 |
| 時(shí)間格式： | HH:MM:SS:hh（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
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19
FN6731.3
November 24, 2008
Once the timer is enabled by setting TMRE=“1”, the TCNT
register is set to “1” and counts up to the TDAT register
value. The TDAT register must has a value of one or greater
in order for the timer to start. If the timer is enabled with
TDAT register less than one, then the timer is disabled and
the TDAT register has to be set to an appropriate value
before the timer can be enabled again. The internal TSCNT
register increments from one, and the incremental frequency
is set by the TCLK[1:0] bits. Once the internal TSCNT
register overflows, the TCNT register will increment by one
and the internal TSCNT register will reset back to one and
start counting again until the TCNT register reaches the
TDAT register value. Once the TCNT register reaches the
TDAT register value, the timer will issue an interrupt that will
set the TMR status bit to “1”. The IRQ2 pin will pulse low for
210ms if the IRQ2E bit is set to “1” for timer interrupt and
TSDAT register is set to “0” for default count value (refer to
Table 10 for the default count values). The timer will reset
and start a new count cycle after the interrupt; therefore, the
watchdog timer is in periodic interrupt mode only with TIM bit
set to “0” or “1”.
The time interval for the watchdog interrupt is calculated
differently for the first watchdog interrupt and for the next
and succeeding watchdog interrupt. For the first watchdog
interrupt (TWD_1st), the time interval is calculated by using
Equation 6. For the next and succeeding watchdog interrupt
(TWD_2nd), the time interval is calculated by using
Equation 7. The low interrupt pulse width of IRQ2 pin
pulse width has a maximum pulse width of 210ms. If the
interrupt is less than 210ms, then the remaining time
(210ms-actual interrupt pulse) from the interrupt pulse width
will be added to the time interval of the next count cycle.
Where, TDAT is the value in the TDAT register. TSDAT is the
value in the TSDAT register (use default if 0). TCLK is the
period set by the TCLK[1:0] bits. For 100Hz setting, please
use 10ms for the period.
Where, TDAT is the value in the TDAT register. TSDAT is the
value in the TSDAT register (use default if 0). TCLK is the
period set by the TCLK[1:0] bits. For 100Hz setting, please
use 10ms for the period.
210ms.
Where, TSDAT is the value in the TSDAT register (use
default if 0). TCLK is the period set by the TCLK[1:0] bits.
For 100Hz setting, please use 10ms for the period.
Power Fail Timer
In Power Fail Timer function, the Timer will start counting
when the device is switched from normal mode to battery
mode.
The power fail timer only works with the TCLK[1:0] setting of
“01”, “10” and “11”. The timer is disabled with the TCLK[1:0]
setting of “00”.
Once the timer is enabled by setting TMRE bit to “1” and the
device switches from normal mode to battery mode, the
TCNT register is set to “1”. The timer expires when TCNT
counts to FFh (255d) and the value in the TDAT register is
ignored.
The internal TSCNT register increments from one, and the
incremental frequency is set by the TCLK[1:0] bits. Once the
internal TSCNT register overflows, the TCNT register
increments by one and the internal TSCNT register resets
back to one and starts counting again until the TCNT register
reaches FFh (255d). Once the TCNT register reaches FFh
(255d), the timer issues an interrupt to set the TMR status bit
to “1” and pull IRQ2 pin low if IRQ2E = “1” (timer interrupt).
The timer stops after the time expires, and the power fail
timer is in single event mode only regarding the status of TIM
bit. The timer restarts and the IRQ2 pin pulls high when the
TMR bit is cleared by the user. The timer can also restart by
resetting the TMRE bit to “1” after setting it to “0” but this
method is not recommended since the TMR status will not
clear by this method and may cause confusion in the
system. In single event mode, the time interval for the timer
expiration is calculated by using Equation 3.
The power fail timer will store the timer value in the TCNT
register after the device switches back to normal mode from
battery mode. The next time the device enters battery mode
from normal mode, the timer will start its count from the
value stored in the TCNT register. The stored value in TCNT
register is only clear when the timer is disabled by setting the
TMRE bit to “0”.
I2C Serial Interface
The ISL12082 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device being controlled is the slave. The master
always initiates data transfers and provides the clock for
both transmit and receive operations. Therefore, the
ISL12082 operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
TWD_1st = TDAT*TSDAT*TCLK
(EQ. 6)
TWD_2nd = (TDAT-1)*TSDAT*TCLK+[(TWD_IRQ)-210ms]
(EQ. 7)
TWD_IRQ(maximum 210ms) = TSDAT*TCLK
(EQ. 8)
ISL12082
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