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參數(shù)資料
| 型號： | ISL12082IB8Z-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC I2C LO-POWER 8-SOIC |
| 標準包裝： | 2,500 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，監(jiān)視計時器 |
| 時間格式： | HH:MM:SS:hh（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
15
FN6731.3
November 24, 2008
alarm register, multiple registers, or all registers can be
enabled for a match.
There are two alarm operation modes: Single Event and
Periodic Interrupt Mode:
Single Event Mode is enabled by setting the ALME bit to
“1”, the IM bit to “0”, and IRQ1E bit to “1” and/or IRQ2E bit
to “0”. This mode permits a one-time match between the
alarm registers and the RTC registers. Once this match
occurs, the ALM status bit is set to “1” and the IRQ1/fOUT
and/or IRQ2 output will be pulled low and will remain low
until the ALM status bit is reset to “0”. This can be done
manually or by using the auto-reset feature.
Periodic Interrupt Mode is enabled by setting the ALME
bit to “1”, the IM bit to “1”, and IRQ1E bit to “1” and/or
IRQ2E bit to “0”. The IRQ1/fOUT and/or IRQ2 output will
now be pulsed each time an alarm occurs. This means
that once the interrupt mode alarm is set, it will continue to
alarm for each occurring match of the alarm and present
time. This mode is convenient for hourly or daily hardware
interrupts in microcontroller applications such as security
cameras or utility meter reading.
To clear an alarm, the ALM status bit must be set to “0” with
a write. Note that if the ARST bit is set to “1” (address 07h,
Bit 7), the ALM bit will automatically be cleared when the
status register is read.
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1 – Alarm set with single interrupt (IM = ”0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm registers as follows:
B. Set the ALME bit as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the ALM bit in the
status register to “1” and also bringing the IRQ1/fOUT and
IRQ2 output low if IRQ1E bit is set to “1” and IRQ2E bit is set
to “0”.
Example 2 – Pulsed interrupt once per minute (IM = ”1”)
Interrupts at one minute intervals when the seconds register
is at 30s.
A. Set alarm registers as follows:
B. Set the Interrupt register as follows:
Once the registers are set, the following waveform will be
seen at IRQ:
Note that the status register ALM bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
Timer Control Register (TMRC) [Address 09h]
TIMER CLOCK FREQUENCY SELECTION BITS
(TCLK <1:0>)
For detailed timer operation, please refer to “TIMER
COUNTER OPERATION” on page 17.
These bits select the Timer/Watchdog clock frequency for
the Timer Counter Register (TCNT, address 13h) and the
internal Sub-Timer Counter Register (TSCNT). When the
ALARM
REGISTER
BIT
DESCRIPTION
76
543210
HEX
SCA
0
000000
00h
Seconds disabled
MNA
1
0
110000
B0h Minutes set to 30,
enabled
HRA
10
010001
91h
Hours set to 11,
enabled
DTA
1
0
000001
81h
Date set to 1,
enabled
MOA
1
0
000001
81h
Month set to 1,
enabled
DWA
0
000000
00h
Day of week
disabled
CONTROL
REGISTER
BIT
DESCRIPTION
7654
3210
HEX
INT
0
1
x
0000
x0hEnable Alarm
NOTE: x indicate other control bits
ALARM
REGISTER
BIT
DESCRIPTION
76543210 HEX
SCA
10110000 B0h Seconds set to 30,
enabled
MNA
00000000 00h Minutes disabled
HRA
00000000 00h Hours disabled
DTA
00000000 00h Date disabled
MOA
00000000 00h Month disabled
DWA
00000000 00h Day of week disabled
CONTROL
REGISTER
BIT
DESCRIPTION
76543210 HEX
INT
1 1 x x 0000
x0hEnable Alarm and Int
Mode
NOTE: x indicate other control bits
TABLE 9. TIMER CONTROL REGISTER (TMRC)
ADDR
7
6
5
4
3
2
1
0
09h
TIM TMRE TMOD1 TMOD0
0
TCLK1 TCLK0
Default
0
60s
RTC AND ALARM REGISTERS ARE BOTH 30s
ISL12082
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