參數(shù)資料
型號(hào)： ISL12082IUZ-T
廠商： Intersil
文件頁(yè)數(shù)： 5/26頁(yè)
文件大?。?/td> 0K
描述： IC RTC I2C LO-POWER 10-MSOP
標(biāo)準(zhǔn)包裝： 2,500
類型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，閏年，監(jiān)視計(jì)時(shí)器
時(shí)間格式： HH:MM:SS:hh（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 2.7 V ~ 5.5 V
電壓 - 電源，電池： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 帶卷 (TR)
13
FN6731.3
November 24, 2008
default setting of this bit is “0” to enable the backup battery
operation. To use the ReSeal function, simply set RESEAL
bit to “1” after the testing is completed. It will enable the
InterSeal Battery Saver mode and prevents battery current
drain before it is first used. Upon the next VDD powerup, the
bit will reset to “0” and the backup battery will be utilized.
CRYSTAL OSCILLATOR ENABLE BIT (XSTOP)
This bit enables/disables the crystal oscillator. When the
XSTOP is set to “1”, the oscillator is disabled. The XSTOP
bit is set to “0” on power-up for normal operation.
AUTO RESET ENABLE BIT (ARST)
This bit enables/disables the automatic reset of the BAT,
ALM and TMR status bits only. When ARST bit is set to “1”,
these status bits are reset to “0” after a valid read of the
respective status register (with a valid STOP condition).
When the ARST is cleared to “0”, the user must manually
reset the BAT, ALM and TMR bits.
Interrupt Control Register (INT) [Address 08h]
FREQUENCY OUT CONTROL BITS (FO <1:0>)
These bits select the output frequency at the IRQ/fOUT pin.
IRQ1E must be set to “0” for frequency output at the
IRQ/fOUT pin. See Table 4 for frequency selection.
Note: The falling edge of 1Hz frequency output is
synchronized with the seconds.
IRQ FUNCTION SELECTION BITS (IRQ1E, IRQ2E)
These bits select the function of IRQ1/fOUT and IRQ2 pin.
See Table 5 for function selection of IRQ1/fOUT pin and
Table 6 for function selection of IRQ2 pin.
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the IRQ1/fOUT pin during battery
backup mode (i.e. VBAT power source active). When the
FOBATB is set to “1”, the IRQ1/fOUT pin is disabled during
battery backup mode. This means that both the frequency
output and alarm output functions are disabled. When the
FOBATB is cleared to “0”, the IRQ1/fOUT pin is enabled
during battery backup mode.
LOW POWER MODE BIT (LPMODE)
This bit enables/disables low power mode. With
LPMODE = “0”, the device will be in normal mode and the
VBAT supply will be used when VDD < VBAT - VBATHYS and
VDD < VTRIP. With LPMODE = “1”, the device will be in low
power mode and the VBAT supply will be used when
VDD <VBAT -VBATHYS. There is a supply current saving of
about 600nA when using LPMODE = “1” with VDD = 5V (See
“Typical Performance Curves” on page 7: IDD vs VCC with
LPMODE ON and OFF). see also “Power Control Operation”
ALARM ENABLE BIT (ALME)
This bit enables/disables the alarm function. When the ALME
bit is set to “1”, the alarm function is enabled. When the ALME
is cleared to “0”, the alarm function is disabled. The alarm
function can operate in either a single event alarm or a periodic
interrupt alarm (see IM bit).
Note: When the frequency output mode is enabled, the alarm
function is disabled.
ALARM PULSE/EVENT INTERRUPT BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
210ms will appear at the IRQ1/fOUT and/or IRQ2 pin when
the RTC is triggered by the alarm as defined by the alarm
registers (0Ch to 11h). When the IM bit is cleared to “0”, the
alarm will operate in standard mode, where the IRQ1/FOUT
and/or IRQ2 pin will be tied low until the ALM status bit is
cleared to “0”. The IM bit is set to “0” on power-up.
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
ADDR
7
6
5
4
3
2
1
0
08h
IM ALME LPMODE FOBATB IRQ2E IRQ1E FO1 FO0
Default
0
TABLE 4. FREQUENCY SELECTION OF fOUT PIN
FREQUENCY,
fOUT
UNITS
FO1
FO0
COMMENT
32768
Hz
0
Free running
crystal clock
4096
Hz
0
1
Free running
crystal clock
512
Hz
1
0
Free running
crystal clock
1
Hz
1
Sync. with
second, 30s jitter
TABLE 5. FUNCTION SELECTION OF IRQ1/fOUT
PIN
IRQ1/fOUT FUNCTION
IRQ2E
IRQ1E
fOUT
X0
ALARM IRQ
X
1
TABLE 6. FUNCTION SELECTION OF IRQ2 PIN
IRQ2 FUNCTION
IRQ2E
IRQ1E
ALARM IRQ
0
X
TIMER IRQ
1
X
IM BIT
ALARM PULSE/EVENT INTERRUPT FUNCTION
0
Single Time Event Set By Alarm
TABLE 5. FUNCTION SELECTION OF IRQ1/fOUT
PIN (Continued)
IRQ1/fOUT FUNCTION
IRQ2E
IRQ1E
ISL12082
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