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參數(shù)資料
型號: ISL1209IU10
廠商: Intersil
文件頁數(shù): 2/24頁
文件大?。?/td> 0K
描述: IC RTC/CALENDAR I2C 10-MSOP
標(biāo)準(zhǔn)包裝: 80
類型: 時間事件記錄器
特點: 警報器,閏年,SRAM
存儲容量: 2B
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
10
FN6109.4
October 17, 2006
Users have the option to connect EVIN (see EVINEB bit) to
an internal pull up current source that operates at 1A
(always on mode). User selectable event sampling modes
are also available which will effectively reduce power
consumption with 1/4-Hz, 1-Hz and 2-Hz sample detection
rates. The EVIN input is pulsed ON/OFF when in sampling
mode for power savings advantages (See tables below).
The EVIN also has a user selectable time based hysteresis
filter (see EHYS bits) to implement switch de-bouncing
during an event detection. The EVIN signal must be high for
the duration of the selected time period. The time periods
available are 0 times delay (no time based hysteresis) to
3.9ms, 15.625ms or 31.25ms (see Table 1, 2, 3, and 4).
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz
quartz crystal to maintain an accurate internal representation
of second, minute, hour, day of week, date, month, and year.
The RTC also has leap-year correction. The clock also
corrects for months having fewer than 31 days and has a bit
that controls 24 hour or AM/PM format. When the ISL1209
powers up after the loss of both VDD and VBAT, the clock will
not begin incrementing until at least one byte is written to the
clock register.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time base
for the RTC. Since the resonant frequency of a crystal is
temperature dependent, the RTC performance will also be
dependent upon temperature. The frequency deviation of
the crystal is a function of the turnover temperature of the
crystal from the crystal’s nominal frequency. For example, a
~20ppm frequency deviation translates into an accuracy of
~1 minute per month. These parameters are available from
the crystal manufacturer. The ISL1209 provides on-chip
crystal compensation networks to adjust load capacitance to
tune oscillator frequency from -94ppm to +140ppm. For
more detailed information see the Application Section.
Single Event and Interrupt
The alarm mode is enabled via the ALME bit. Choosing
single event or interrupt alarm mode is selected via the IM
bit. Note that when the frequency output function is enabled,
the alarm function is disabled.
The standard alarm allows for alarms of time, date, day of
the week, month, and year. When a time alarm occurs in
single event mode, an IRQ pin will be pulled low and the
alarm status bit (ALM) will be set to “1”.
The pulsed interrupt mode allows for repetitive or recurring
alarm functionality. Hence, once the alarm is set, the device
will continue to alarm for each occurring match of the alarm
and present time. Thus, it will alarm as often as every minute
(if only the nth second is set) or as infrequently as once a
year (if at least the nth month is set). During pulsed interrupt
mode, the IRQ pin will be pulled low for 250ms and the alarm
status bit (ALM) will be set to “1”.
The ALM bit can be reset by the user or cleared
automatically using the auto reset mode (see ARST bit).
The alarm function can be enabled/disabled during battery
backup mode using the FOBATB bit. For more information
on the alarm, please see the Alarm Registers Description.
Frequency Output Mode
The ISL1209 has the option to provide a frequency output
signal using the IRQ/FOUT pin. The frequency output mode
is set by using the FO bits to select 15 possible output
frequency values from 0 to 32kHz. The frequency output can
be enabled/disabled during battery backup mode using the
FOBATB bit.
General Purpose User SRAM
The ISL1209 provides 2 bytes of user SRAM. The SRAM will
continue to operate in battery backup mode. However, it
should be noted that the I2C bus is disabled in battery
backup mode.
TABLE 1.
IDD (VDD=3V, tHYS=3.9ms)
fSMP
DELTA IDD
1/4Hz
20.5nA
1Hz
82nA
2Hz
164nA
TABLE 2.
IDD (VDD=5.0V, tHYS=3.9ms)
fSMP
DELTA IDD
1/4Hz
65.8nA
1Hz
263.3nA
2Hz
526.5nA
TABLE 3.
IDD (VDD=3.0V, tHYS=15.625ms)
fSMP
DELTA IDD
1/4Hz
82nA
1Hz
328nA
2Hz
656.3nA
TABLE 4.
IDD (VDD=5.0V, tHYS=15.625ms)
fSMP
DELTA IDD
1/4Hz
264nA
1Hz
1.05A
2Hz
2.1A
ISL1209
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