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參數(shù)資料
| 型號： | ISL1539AIRZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VDSL2 LINE DVR AMP 24QFN |
| 標準包裝： | 90 |
| 類型： | 驅(qū)動器 |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | VDSL2 |
| 電源電壓： | ±5 V ~ 15 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN（5x4） |
| 包裝： | 管件 |
19
FN6916.0
September 23, 2009
Assuming Rf = 3kΩ, Rg = 333Ω, Rb = 7.5kΩ Rcm = 5kΩ,
the total output offset voltage derived is expressed in
Equation 12:
Given the worst case DC errors, 434mV of DC shift will
be at the output reducing the available output swing
slightly. Actual operation should never see this much
shift as the error terms are not completely
independent.
Output Headroom Model
Driving high voltages into heavy loads will require a
careful consideration of the available output swing vs.
load. Figure 48 shows a useful model for predicting the
available output swing. If the output is modeled as ideal
NPN and PNP transistors, the output swing limits can be
described as no load headrooms (VP and VN) and an
equivalent impedance to the supplies (RP and RN)
The no load headrooms can be found in the “Electrical
Specifications” table on page 5 as 12V - 10.9V = 1.1V
and they are equal to each supply.
The equivalent impedances for this model can be
extracted from the reduced swings shown in the
specification table for the heavier loads. Looking at the
typical 60Ω load swings, we see a +9.8V and -9.7V
swing. Solving for the two resistors in the Headroom
model shown in Figure 48 gives:
Rp = 6.7Ω and Rn = 7.4Ω.
For the differential configuration, Figure 49 shows the
Headroom model that can be used to predict the
maximum available swing for a given supply voltage and
load resistor, RL.
For equal bipolar supplies, the available peak output
swing will be given by Equation 13:
For example, to worst case the typical gain of 10 design
using ±12V supplies with ±5% supply tolerance and a
minimum expected load of 90Ω, a maximum VP can be
calculated as shown in Equation 14:
The minimum VP-P would be twice this, or 31.8VP-P.
While this extreme condition would normally not be
encountered, it does show the importance of knowing
your minimum expected load for high output swing
conditions.
Output Noise Model
The full differential output noise model for the ISL1539A
should include the 3 input noise terms for each device as
well as the noise contributions due to the external
resistors.
This necessarily becomes an involved model due to the
number of terms, but if the terms that are the same on
each side of the differential circuit can be assumed to be
equal, it will simplify considerably. The noise model
shown in Figure 50 includes all of the op amp terms and
resistor terms. This model is directed at calculating the
differential output spot noise for different values of the
resistors in the simple differential gain circuit. It is
assuming each amplifier term is independent and
uncorrelated to the other terms.
Vcm
Vocm
0.5
Vodm
×
+
434mV
==
(EQ. 12)
FIGURE 48. HEADROOM MODEL
+
–
+
–
+VS
-VS
RP
RN
RL
VP
VN
+/-VO
FIGURE 49. HEADROOM MODEL
-
+
-
+
RL
VP
+VS
-VS
L
n
p
n
p
s
p
R
V
+
=
1
)
(
2
(EQ. 13)
p
L
n
p
n
p
s
p
V
R
V
9
.
15
90
4
.
7
.
6
1
)
2
.
2
4
.
11
(
2
1
)
(
2
=
Ω
+
Ω
+
=
+
=
(EQ. 14)
ISL1539A
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