參數(shù)資料
型號: ISL22102IV20Z
廠商: Intersil
文件頁數(shù): 9/11頁
文件大?。?/td> 0K
描述: IC POT DUAL 32TAP 20-TSSOP
標(biāo)準(zhǔn)包裝: 740
系列: XDCP™
接片: 32
電阻(歐姆): 18.5k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 10 ppm/°C
存儲(chǔ)器類型: 易失
接口: 2 線按鈕
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
7
FN6788.1
January 14, 2010
Pin Descriptions
LEFT_IN, RIGHT_IN
The LEFT_IN and RIGHT_IN pins of the ISL22102 are
equivalent to the fixed terminals of a mechanical
potentiometer. The stereo audio signal applied to these pins
are referenced to VB and may have ±AVCC/2 maximum
amplitude.
LEFT_OUT, RIGHT_OUT
The LEFT_OUT and RIGHT_OUT pins are the buffered
wiper terminals of the potentiometers which are equivalent to
the movable terminals of a mechanical potentiometers with
attached unity gain operational amplifiers (Op Amp). The
default output position of wiper terminals preset to -20dB
attenuation of input signals.
VB
This is reference voltage output equal AVCC/2. It is used as
common point for audio inputs, as well as reference signal
for other system components.
UP
The debounced active low UP input is increment the wipers
position of both channels. An on-chip 2A current source
pull-up holds the UP input High. A switch closure to ground
or a Low logic level will after a debounce time and Zero
Amplitude Crossing Detection, move the wiper to the next
adjacent higher tap position. If the UP input signal is held
down for 1s, the wipers will auto increment their position with
a 4Hz frequency rate for 4s, and then a 8Hz frequency rate
(see Figure 2). When the wipers reach their top position of
0dB attenuation, they will stay at this position ignoring any
further Up commands.
DN
The debounced DN input is decrement the wipers position of
both channels. An on-chip 2A current source pull-up holds
the DN input High. A switch closure to ground or a Low logic
level will, after a debounce time and Zero Amplitude
Crossing Detection, move the wiper to the next adjacent
lower tap position. If DN input signal is held down for 1s, the
wipers will auto decrement their position with a 4Hz
frequency rate for 4s, and then a 8Hz frequency rate. When
the wipers reach their bottom position of -90dB attenuation,
they will stay at this position ignoring any further Down or
Mute commands.
MUTE
The first active low MUTE input pulse allows both wipers to
move, after a debounce time and Zero Amplitude Crossing
Detection, to the highest attenuation level of -90dB in one
step. The second active low MUTE pulse will return both
wipers to their original position, prior to MUTE command. An
on-chip 2A current source pull-up holds the MUTE input
High.
SB
The active low SB input allows totally disconnect DCP arrays
from their LEFT_IN and RIGHT_IN pins, and move both
wipers to position closest to VB pin (as shown in Figure 3). It
also sets ISL22102 in low power Standby mode. When SB
will be released, the both wipers will be set at position they
have prior Standby.
.
FLAG
This output pin provides status information to the rest of the
system about audio activity. It is High when at least one
audio input exceeds VTH threshold, otherwise its output level
is Low. The FLAG output can be directly connected to SB pin
for automatical setting the ISL22102 in Standby mode.
D0-D2
These three digital input pins allow to program a delay time
for FLAG Low output up to 240s. Table 1 lists the D0-D2
settings and corresponding delay times (typical values).
CB
This low pass filter terminal requires an external capacitor to
GND. The value of this capacitor, together with 5M
Ω internal
resistor divider, directly determines the PSRR (Power Supply
Rejection Ratio) of audio and VB outputs. A 1F to 10F
capacitor is recommended.
HPA, HPB
These two high pass filter terminals require an external
capacitor of 100nF or higher in-between.
TABLE 1. FLAG PROGRAMMED DELAY SETTINGS
D2
D1
D0
DELAY, (s)
000
0
001
60
010
90
011
120
100
150
101
180
110
210
111
240
VB
WIPER_LEFT
LEFT_IN
FIGURE 3. DCP CONNECTION IN STANDBY MODE
(RIGHT_IN)
(WIPER_RIGHT)
ISL22102
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