7 FN7780.1 August 16, 2011 tDCP Wiper Response Time W option; CS rising edge to wiper n" />
參數(shù)資料
型號(hào): ISL23415WFUZ-T7A
廠商: Intersil
文件頁(yè)數(shù): 18/20頁(yè)
文件大?。?/td> 0K
描述: IC DGTL POT 256POS 10K 10MSOP
產(chǎn)品培訓(xùn)模塊: Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝: 1
系列: XDCP™
接片: 256
電阻(歐姆): 10k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 175 ppm/°C
存儲(chǔ)器類型: 易失
接口: 4 線 SPI(芯片選擇)
電源電壓: 1.2 V ~ 5.5 V,1.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ISL23415WFUZ-T7ADKR
ISL23415
7
FN7780.1
August 16, 2011
tDCP
Wiper Response Time
W option; CS rising edge to wiper new position,
from 10% to 90% of final value.
0.4
s
U option; CS rising edge to wiper new position,
from 10% to 90% of final value.
1.5
s
T option; CS rising edge to wiper new position,
from 10% to 90% of final value.
3.5
s
tShdnRec
DCP Recall Time From Shutdown Mode
CS rising edge to wiper recalled position and
RH connection
1.5
s
VCC, VLOGIC
Ramp
VCC, VLOGIC Ramp Rate
Ramp monotonic at any level
0.01
50
V/ms
Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20)
UNITS
Serial Interface Specification For SCK, SDI, SDO, CS Unless Otherwise Noted.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20)
UNITS
VIL
Input LOW Voltage
-0.3
0.3 x VLOGIC
V
VIH
Input HIGH Voltage
0.7 x VLOGIC
VLOGIC+ 0.3
V
Hysteresis
SDI and SCK Input Buffer Hysteresis
VLOGIC > 2V
0.05 x VLOGIC
V
VLOGIC < 2V
0.1 x VLOGIC
VOL
SDO Output Buffer LOW Voltage
IOL = 3mA, VLOGIC > 2V
0
0.4
V
IOL = 1.5mA, VLOGIC < 2V
0.2 x VLOGIC
V
Rpu
(Note 19)
SDO Pull-up Resistor Off-chip
Maximum is determined by tRO and tFO with
maximum bus load Cb = 30pF, fSCK =5MHz
1.5
k
Ω
Cpin
SCK, SDO, SDI, CS Pin Capacitance
10
pF
fSCK
SCK Frequency
VLOGIC = 1.7V to 5.5V
5
MHz
VLOGIC = 1.2V to 1.6V
1
MHz
tCYC
SPI Clock Cycle Time
VLOGIC ≥ 1.7V
200
ns
tWH
SPI Clock High Time
VLOGIC ≥ 1.7V
100
ns
tWL
SPI Clock Low Time
VLOGIC ≥ 1.7V
100
ns
tLEAD
Lead Time
VLOGIC ≥ 1.7V
250
ns
tLAG
Lag Time
VLOGIC ≥ 1.7V
250
ns
tSU
SDI, SCK and CS Input Setup Time
VLOGIC ≥ 1.7V
50
ns
tH
SDI, SCK and CS Input Hold Time
VLOGIC ≥ 1.7V
50
ns
tRI
SDI, SCK and CS Input Rise Time
VLOGIC ≥ 1.7V
10
ns
tFI
SDI, SCK and CS Input Fall Time
VLOGIC ≥ 1.7V
10
20
ns
tDIS
SDO Output Disable Time
VLOGIC ≥ 1.7V
0
100
ns
tSO
SDO Output Setup Time
VLOGIC ≥ 1.7V
50
ns
tV
SDO Output Valid Time
VLOGIC ≥ 1.7V
150
ns
tHO
SDO Output Hold Time
VLOGIC ≥ 1.7V
0
ns
tRO
SDO Output Rise Time
Rpu = 1.5k, Cbus = 30pF
60
ns
tFO
SDO Output Fall Time
Rpu = 1.5k, Cbus = 30pF
60
ns
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