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參數(shù)資料
| 型號： | ISL26313FBZ-T7A |
| 廠商： | Intersil |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SPI/SRL 125K 8SOIC |
| 標準包裝： | 250 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 125k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 80mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極 |
ISL26310, ISL26311, ISL26312, ISL26313, ISL26314, ISL26315, ISL26319
16
FN7549.2
February 26, 2014
Serial Digital Interface
The ISL26310, ISL26311, ISL26312, ISL26313, ISL26314,
ISL26315 and ISL26319 families are utilizes an SPI-compatible
interface to set the device configuration and read conversion
data. This flexible interface provides 3 modes of operation:
Reading After Conversion (RAC), Reading During Conversion
(RDC), and Reading Spanning Conversions (RSC), with an
additional option providing an End of Conversion (EOC) indication
on the SDO output in all 3 modes. The choice of operating mode
is determined by the timing of the signals on the serial interface.
The interface consists of the data clock (SCLK), serial digital
input (SDI), serial digital output (SDO), and the conversion control
input (CNV). From the Idle state (after completion of a prior
conversion), a High-to-Low transition on CNV indicates the
beginning of input signal acquisition, with the Conversion then
initiated by a subsequent Low-to-High transition. When CNV is
Low, input data presented to SDI is latched on the rising edge of
SCLK. Output data will be present at SDO on the falling edge of
SCLK. SDO is in the high-impedance state whenever CNV is High,
and activity on SCLK should be avoided during this time to avoid
corruption of the conversion process. SCLK should be Low when
CNV is High.
During the Nth conversion, output data indicates the conversion
data and configuration settings for the N-1th conversion, while
the current configuration settings apply to the N+1th conversion.
In order to minimize errors due to digital noise coupling, there
should be no activity on the serial interface after the specified
tDATA period. Data should be read before the conversion is
completed to avoid the newer results being overwritten resulting
in a permanent loss of data.
Reading After Conversion Mode Without EOC
In this mode, data transfer always occurs during the Acquisition
phase, supporting the widest variety of interface data rates.
Figure 30 depicts a timing waveform in this mode. From Idle, the
device enters the Acquisition phase when CNV is taken Low. SDO
emerges High from a high-impedance state, waiting for an SCLK
to present the MSB of the current output data word. The
configuration settings can be updated using SDI and at the same
time previous conversion results can be read from SDO. After the
communication is completed or the required acquisition time
(tACQ) has elapsed – whichever is later – CNV transitions High
indicating the start of conversion. CNV must be held High
continuously for a minimum of 7.2s (at 125kSPS) so that the
conversion is completed without enabling EOC. Subsequently
CNV may be asserted Low at any time so that the next
Acquisition phase can begin. This method is suitable for hosts
which operate with lower frequency SCLK.
Note that when using slower SPI rates the data transfer time can
exceed the minimum acquisition time, which will limit the
conversion throughput to less than the maximum specified rate.
For example, a 12-bit data transfer takes 12s with a 1MHz SPI
clock. This adds to the 7.2s conversion time for an effective
throughput of 52ksps.
Reading During Conversion Mode
Without EOC
From Idle, the user initiates the input signal Acquisition mode by
taking CNV Low, and then initiates a conversion after tACQ by
pulsing CNV High. After the conversion starts, data is exchanged
on the serial interface while CNV is held Low (see Figure 31). CNV
must also be asserted High before tDATA to avoid enabling EOC.
This method is ideal for hosts with high SCLK communication
rates to operate the device at the highest conversion rates.
At the end of conversion the device enters the Idle state. After the
host is certain that the conversion is completed (7.2s after
conversion is initiated at 125kSPS) a new acquisition can be
initiated by pulling CNV Low which will initiate the Acquisition state.
Reading Spanning Conversion Mode
Without EOC
In applications desiring slower interface data rates and while still
maintaining maximum possible throughput, RSC mode can be
used to transfer data during both the Acquisition and Conversion
phases, as shown in Figure 32.
Data exchange begins during the Acquisition phase until CNV is
asserted High to initiate a conversion and SDO returns to the
high-impedance state, interrupting the exchange. After CNV is
returned Low, SDO will return to the state prior to the CNV pulse
in order to avoid data loss. Once again data exchange occurs
when CNV is Low. CNV must be asserted High before tDATA in
order to avoid enabling EOC.
At the end of conversion the device enters the Idle state. After
the host is certain that the conversion is completed (7.2s after
conversion is initiated at 125kSPS) a new acquisition can be
initiated by pulling CNV Low, which will take the device back to
Acquisition state from Idle state.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL26314 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-bit, 125kSPS Low-power ADCs with Single-ended and Differential Inputs and Multiple Input Channels |
| ISL26314FVZ | 制造商:Intersil Corporation 功能描述:ISL26314FVZ 12-BIT, 125KSPS, 4-CHANNEL, DIFFERENTIAL SAR ADC - Rail/Tube |
| ISL26314FVZ-T | 制造商:Intersil Corporation 功能描述:ISL26314FVZ 12-BIT, 125KSPS, 4-CHANNEL, DIFFERENTIAL SAR ADC - Tape and Reel |
| ISL26314FVZ-T7A | 功能描述:IC ADC 12BIT SRL/SPI 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 位數(shù):10 采樣率（每秒）:357k 數(shù)據(jù)接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:830µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:10-WFDFN 裸露焊盤 供應商設(shè)備封裝:10-TDFN-EP（3x3） 包裝:剪切帶 (CT) 輸入數(shù)目和類型:2 個單端，單極；2 個單端，雙極；1 個差分，單極；1 個差分，雙極 產(chǎn)品目錄頁面:1396 (CN2011-ZH PDF) 其它名稱:MAX1395ETB+TCT |
| ISL26315 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-bit, 125kSPS Low-power ADCs with Single-ended and Differential Inputs and Multiple Input Channels |
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