15 FN7999.3 September 5, 2012 Converter Operation The ISL26712, ISL26710 and ISL26708 are designed to minimize pow" />
參數(shù)資料
型號: ISL26708IRTZ-T
廠商: Intersil
文件頁數(shù): 7/21頁
文件大?。?/td> 0K
描述: IC ADC 8BIT SAR 1MSPS 8-TDFN
標(biāo)準(zhǔn)包裝: 6,000
位數(shù): 8
采樣率(每秒): 1M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 8.5mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-WDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-TDFN(3x3)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,單極
ISL26712, ISL26710, ISL26708
15
FN7999.3
September 5, 2012
Converter Operation
The ISL26712, ISL26710 and ISL26708 are designed to
minimize power consumption by only powering up the SAR
comparator during conversion time. When the converter is in
track mode (its sample capacitors are tracking the input signal)
the SAR comparator is powered down. The state of the converter
is dictated by the logic state of CS. When CS is high the SAR
comparator is powered down while the sampling capacitor array
is tracking the input. When CS transitions low, the capacitor array
immediately captures the analog signal that is being tracked.
After CS is taken low, the SCLK pin is toggled 16 times. For the
first 3 clocks, the comparator is powered up and auto-zeroed,
then the SAR decision process is begun. This process uses 12
SCLK cycles for the 12-bit ISL26712. Each SAR decision is
presented to the SDATA output on the next clock cycle after the
SAR decision is performed. The SAR process (12 bits) is
completed on SCLK cycle 15. At this point in time, the SAR
comparator is powered down and the capacitor array is placed
back into Track mode. The last SAR comparator decision is
output from SDATA on the 16th SCLK cycle. When the last data
bit is output from SDATA the output switches to a logic 0 until CS
is taken high, at which time, the SDATA output enters a High-Z
state.
The ISL26710 and ISL26708 will take fewer clock cycles for their
SAR decisions and will output fewer data bits. The extra bits
following the output of the LSB will be logic zeroes.
Figures 32, 33, and 34 illustrate the system timing for the 12-,
10- and 8-bit converters respectively.
FIGURE 30. PRECISION VOLTAGE REFERENCE FOR +5V SUPPLY
1
2
3
4
8
7
6
5
DNC
VIN
COMP
GND
DNC
VOUT
TRIM
0.1F
VDD
0.1F
2.5V
VREF
0.1F
BULK
+
5V
ISL21090
ISL267440
ISL267450A
FIGURE 31. VOLTAGE REFERENCE FOR +2.7V TO +3.6V, OR FOR +5V SUPPLY
ISL267817
VDD
0.1F
VREF
0.1F
BULK
+
+2.7V TO +3.6V
ISL21010
GND
VIN
VOUT
1
2
3
0.1F
1.25, 2.048 OR 2.5V
OR +5V
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