參數(shù)資料
型號(hào)： XRT91L32IQTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 1/37頁(yè)
文件大?。?/td> 0K
描述： IC TXRX SONET/SDH 8BIT 100QFP
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 收發(fā)器
規(guī)程： SONET/SDH
電源電壓： 3.3V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-QFP（14x20）
包裝： 帶卷 (TR)
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
xr
XRT91L32
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
JUNE 2007
REV. 1.0.3
GENERAL DESCRIPTION
The XRT91L32 is a fully integrated SONET/SDH
transceiver for SONET/SDH 622.08 Mbps STS-12/
STM-4 or 155.52 Mbps STS-3/STM-1 applications.
The transceiver includes an on-chip Clock Multiplier
Unit (CMU), which uses a high frequency Phase-
Locked Loop (PLL) to generate the high-speed
transmit serial clock from a slower external clock
reference. It also provides Clock and Data Recovery
(CDR) function by synchronizing its on-chip Voltage
Controlled Oscillator (VCO) to the incoming serial
data stream. The internal CDR unit can be disabled
and bypassed in lieu of an externally recovered
received clock from the optical module. Either the
internally recovered clock or the externally recovered
clock can be used for loop timing applications. The
chip provides serial-to-parallel and parallel-to-serial
converters using an 8-bit wide LVTTL system
interface in both receive and transmit directions.
The transmit section includes an option to accept a
parallel clock signal from the framer/mapper to
synchronize the transmit section timing. The device
can internally monitor Loss of Signal (LOS) condition
and automatically mute received data upon LOS. An
on-chip SONET/SDH frame byte and boundary
detector and frame pulse generator offers the ability
recover SONET/SDH framing and to byte align the
receive serial data stream into the 8-bit parallel bus.
APPLICATIONS
SONET/SDH-based Transmission Systems
Add/Drop Multiplexers
Cross Connect Equipment
ATM and Multi-Service Switches, Routers and
Switch/Routers
DSLAMS
SONET/SDH Test Equipment
DWDM Termination Equipment
FIGURE 1. BLOCK DIAGRAM OF XRT91L32
XRT91L32
Re
se
t
DL
O
P
RL
O
P
S
LO
OP
T
IM
E
L
O
SEXT
ST
S-
1
2
/S
T
S
-3
A
L
OOP
DL
O
S
DIS
F
R
AM
EPU
L
S
E
OO
F
Clock Control
Control Block
CDRD
IS
CDR
RE
F
S
E
L
CM
UF
RE
Q
S
E
L
STS-12/STM-4 or STS-3/STM-1
TRANSCEIVER
Loop Filters
CA
P
1
P
CA
P
2
P
C
AP1
N
C
AP2
N
RXDO[7:0]
RXPCLKO
CDR
RXIP/N
8
Div by 8
XRXCLKIP/N
SIPO
(Serial Input
Parallel Output)
MU
X
PISO
(Parallel Input
Serial Output)
DLOOP
RLOOPS
Re-Timer
CMU
TXOP/N
MU
X
XO
R
TTLREFCLK
REFCLKP/N
CDRAUXREFCLK
MU
X
TXPCLK_IO
Div by
8
ENB
TXDI[7:0]
8
MU
X
ALOOP
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