參數(shù)資料
型號: ISL28272FAZ
廠商: Intersil
文件頁數(shù): 2/14頁
文件大?。?/td> 0K
描述: IC INSTR AMP RRIO SGL 16-QSOP
標(biāo)準(zhǔn)包裝: 97
放大器類型: 儀表
電路數(shù): 2
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 0.5 V/µs
-3db帶寬: 100kHz
電流 - 輸入偏壓: 10pA
電壓 - 輸入偏移: 35µV
電流 - 電源: 120µA
電流 - 輸出 / 通道: 31mA
電壓 - 電源,單路/雙路(±): 2.4 V ~ 5.5 V,±1.2 V ~ 2.75 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 管件
10
FN6390.2
August 17, 2007
Pin Descriptions
ISL28271
16 Ld QSOP
ISL28272
16 Ld QSOP
PIN NAME
EQUIVALENT
CIRCUIT
PIN FUNCTION
2, 15
OUT_A,
OUT_B
Circuit 3
Output Voltage. A complementary Class AB common-source output stage drives
the output of each channel. When disabled, the outputs are in a high impedance
state.
3, 14
FB+_A,
FB+_B
Circuit 1A,
Circuit 1B
Positive Feedback high impedance terminals. ISL28272 input circuit is shown in
Circuit 1A, and the ISL28271 input circuit is shown in Circuit 1B.
ISL28271: to avoid offset drift, it is recommended that the terminals of the
ISL28271 are not overdriven beyond 1V and the input current must never
exceed 5mA.
4, 13
FB-_A,
FB-_B
Circuit 1A,
Circuit 1B
Negative Feedback high impedance terminals. The FB- pins connect to an
external resistor divider to individually set the desired gain of the in-amp.
ISL28272 input circuit is shown in Circuit 1A, and the ISL28271 input circuit is
shown in Circuit 1B.
ISL28271: to avoid offset drift, it is recommended that the terminals of the
ISL28271 are not overdriven beyond 1V and the input current must never
exceed 5mA.
5, 12
IN-_A,
IN-_B
Circuit 1A,
Circuit 1B
High impedance Inverting input terminals. Connect to the low side of the input
source signal. ISL28272 input circuit is shown in Circuit 1A, and the ISL28271
input circuit is shown in Circuit 1B.
ISL28271: to avoid offset drift, it is recommended that the terminals of the
ISL28271 are not overdriven beyond 1V and the input current must never
exceed 5mA.
6, 11
IN+_A,
IN+_B
Circuit 1A,
Circuit 1B
High impedance Non-inverting input terminals. Connect to the high side of the
input source signal. ISL28272 input circuit is shown in Circuit 1A, and the
ISL28271 input circuit is shown in Circuit 1B.
ISL28271: to avoid offset drift, it is recommended that the terminals of the
ISL28271 are not overdriven beyond 1V and the input current must never
exceed 5mA.
7, 10
EN_A,
EN_B
Circuit 2
Active LOW logic pins. When pulled above 2V, the corresponding channel turns
off and OUT is high impedance. A channel is enabled when pulled below 0.8V.
Built-in pull downs define each EN pin LOW when left floating.
16
V+
Circuit 4
Positive Supply terminal shared by all channels.
8
V-
Circuit 4
Negative Supply terminal shared by all channels. Grounded for single supply
operation.
1, 9
NC
No Connect, pins can be left floating or grounded.
IN-
V+
V-
LOGIC
PIN
V+
V-
V+
V-
OUT
CIRCUIT 3
CIRCUIT 1A
CIRCUIT 2
V+
V-
CAPACITIVELY
COUPLED
ESD CLAMP
CIRCUIT 4
V+
V-
CIRCUIT 1B
FB-
IN-
FB-
IN+
FB+
IN+
FB+
ISL28271, ISL28272
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