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| 型號(hào)： | ISL28617FVZ-T7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INSTRUMENTATION AMP 24TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 放大器類型： | 儀表 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分，滿擺幅 |
| 轉(zhuǎn)換速率： | 4 V/µs |
| -3db帶寬： | 5.5MHz |
| 電流 - 輸入偏壓： | 200pA |
| 電壓 - 輸入偏移： | 30µV |
| 電流 - 電源： | 2.05mA |
| 電流 - 輸出 / 通道： | 45mA |
| 電壓 - 電源，單路/雙路(±)： | 8 V ~ 40 V，±4 V ~ 20 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
ISL28617
17
FN6562.1
October 17, 2013
Reduced trace lengths that maintain DC accuracy are also
important for minimizing the capacitance that can degrade AC
stability. This is especially true at gains less then 1. Layout
techniques for precision applications using larger size precision
gain resistors at very low gains (G = 0.1V/V) include removing a
section of the underlying PC ground plane directly under the gain
resistor terminals and body.
Layout guidelines for high CMRR include matching trace lengths
and symmetrical component placement on the circuit that
connects the signal source to the IN+ and IN- pins. This ensures
matching of the IN+ and IN- input impedances (Figure 34).
Power Supply Decoupling
Standard power supply decoupling consists of a single 0.1F
50V ceramic capacitor at the power supply terminals located as
close to the device as possible. In applications where the input
and output supplies are strapped to the same voltage (VEE = VEO,
VCC = VCO) the connection point should be as close to the device
as possible, with a single 0.1F 50V ceramic capacitor at the
junction. Applications using separate supplies require 0.1F 50V
ceramic decoupling capacitors at each power supply terminal.
3. Estimating Amplifier DC and Noise
Performance
The gain resistor ohmic values and ratios are all that is required
to estimate DC offset and noise. The following sections illustrate
methods to calculate DC offset and noise performance. These
estimates are useful for optimizing resistor values for noise and
DC offset.
Calculating DC Offset Voltage
Output offset voltage, like output noise, has several contributors.
Also similar to output noise, the major offset contributor depends
on the gain configuration. In high-gain, VOS(I) dominates, while in
low-gain, offset due to IERR dominates.
The summation of DC offsets to arrive at total DC offset error is
performed in two ways. Equation 13 is a simple addition of the
DC offsets appearing at the output, and is useful when defining
the minimum to maximum range of offset that can be expected.
The drawback is that the result defines the corner of the corner
of the error box, and not a typical value given that these sources
are uncorrelated.
Equation 14 expresses the total DC error as the rms, or square
root of the sum of the squares to provide an estimate of a typical
value.
to an input referred error range [VOS(RTI)] and enables a
comparison with the DC component of the input signal.
Similarly, Equation 16 shows the typical DC offset value
(Equation 14) referred to the input.
NOTE: These results are summarized in Table 1.
Calculating Noise Voltage
The calculation of noise spectral density at the output [eN(RTO)]
converts the output noise to the input referred value when
evaluating the input signal to noise ratio.
Table 2 provides examples of the noise contribution of each
source by circuit gain and output voltage span. In a high-gain
configuration, the input noise is the dominant noise source. In a
low-gain configuration, the noise voltage from the product of the
internal noise current, IN(err), and the feedback resistor, RFB
dominates. The contribution of the internal noise current, IN(err)
increases in proportion to RFB, but the corresponding increase in
output voltage with RFB keeps the ratio of this noise voltage to
output voltage constant.
(EQ. 13)
VOS(RTO) = [(AV × VOS(I)) + (VOS(FB)) + (IERR × RFB)]
(EQ. 14)
VOS(RTO)TYP = √[(AV×VOS(I))+(VOS(FB))+(IERR×RFB)]
(EQ. 15)
VOS(RTI) = [(VOS(I)) + (VOS(FB)/AV) + (IERR × RFB)/AV]
(EQ. 16)
VOS(RTI)TYP = √[VOS(I)) + (VOS(FB)/AV) + (IERR × RFB)/AV)]
(EQ. 17)
eN(RTO) = √[(AV × eN(I)) + (2 × AV × iN(I) × 500Ω) +
(AV) x (4kT × RIN) + (4kT × RFB) + (RFB × iN(IERR))+(eN(FB))]
(EQ. 18)
eN(RTI) = eN(RTO)/AV
TABLE 1. COMPUTING TYPICAL OUTPUT OFFSET VOLTAGE RANGES
AV
VO(LIN)
RIN
(k
Ω)
RFB
(k
Ω)
AV x VOS(I)
(V)
(Note 11)
VOS(FB)
(V)
(Note 11)
IERR (5nA)
x RFB
(V)
(Note 11)
VOS(RTO)
(V)
Equation 13
VOS(RTI)
(V)
Equation 15
TYPICAL
VOS(RTO)
(V)
Equation 14
TYPICAL
VOS(RTI)
(V)
Equation 16
1
±2.5
30
±30
±400
±150
±580
428
1
±10
120
±15
±400
±600
±1015
721
100
±2.5
0.3
30
±1500
±400
±150
±2000
±20
1560
15.6
100
±10
1.2
120
±1500
±400
±600
±2500
±25
1669
16.7
NOTE:
11. Chosen for illustration purposes and does not reflect actual device performance.
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