Group driver output enables, that are internally pulled high to V
參數(shù)資料
型號: ISL32272EIVZ
廠商: Intersil
文件頁數(shù): 15/20頁
文件大?。?/td> 0K
描述: IC TX RS422 QUAD 16TSSOP
標(biāo)準(zhǔn)包裝: 96
類型: 發(fā)射器
驅(qū)動器/接收器數(shù): 4/0
規(guī)程: RS422
電源電壓: 3 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 散裝
4
FN6824.1
March 13, 2013
Pin Descriptions
PIN
FUNCTION
EN, EN
Group driver output enables, that are internally pulled high to VCC. All ISL32x72E driver outputs, Y and Z, are enabled by driving EN
high OR EN low, and the outputs are high impedance when EN is low AND EN is high (i.e., if using only the active high EN, connect
EN directly to VCC or VL; if using only the active low EN, connect EN directly to GND). On the ISL32179E accomplish group enable
by connecting all the ENX pins to VCC or VL, and then use the EN or EN pin as previously described. If the group driver enable
function isn’t required (see Note), connect EN to VCC, or connect EN to GND. (ISL32x72E and ISL32179E only)
EN12,
EN34
Paired driver output enables, that are internally pulled high to VCC. Driving EN12 (EN34) high enables Channel 1 and 2 (3 and 4)
outputs (Y and Z). Driving EN12 (EN34) low disables Channel 1 and 2 (3 and 4) outputs. If the driver enable function isn’t required
(see Note), connect EN12 and EN34 to VCC. (ISL32x74E only)
ENx
Individual driver output enables that are internally pulled high to VCC. Forcing ENx high (along with EN high OR EN low) enables the
channel X outputs (Y and Z). Driving ENX low disables the Channel X outputs, regardless of the states of EN and EN. Connect both
EN and EN to VCC for the lowest SHDN current if utilizing SHDN mode (see SHDNEN below). If the individual driver enable function
isn’t required (see Note), connect ENX to VCC. (ISL32179E only)
SHDNEN
Low power SHDN mode enable. A high level allows the ISL32179E to enter a low power mode when all channels are disabled. A low
level prevents the device from entering the low power mode. (ISL32179E only)
DIx
Driver input. A low on DI forces the corresponding channel’s output Y low and output Z high. Similarly, a high on DI forces output Y
high and output Z low.
SPA, SPB
Speed select inputs that are internally pulled-high. See ISL32179E Truth Table on page 3. (ISL32179E only)
GND
Ground connection. This is also the potential of the QFN thermal pad.
Yx
±16.5kV IEC61000-4-2 ESD Protected RS-422 level, noninverting transmitter output.
Zx
±16.5kV IEC61000-4-2 ESD Protected RS-422 level, inverting transmitter output.
VCC
System power supply input (3.0V to 5.5V). On devices with a VL pin powered from a separate supply, power-up VCC first.
VL
Logic power supply input. Connecting the VL pin to the lower voltage power supply of a logic device (e.g., UART or controller)
interfacing with the ISL32179E tailors its logic pin (DI, EN (all varieties), SHDNEN, and SP) VIL/VIH levels to values compatible with
the lower supply voltage. If VL and VCC are different supplies, power-up this supply after VCC, and keep VL ≤ VCC. (ISL32179E only)
EP
Thermal Pad. Connect the EP to GND. (ISL32179E only)
NOTE: Unused EN pins of any type should not be left floating, even though they have internal pull-ups.
ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E
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