14 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the qual" />
參數(shù)資料
型號: ISL33001IUZ-T
廠商: Intersil
文件頁數(shù): 6/18頁
文件大?。?/td> 0K
描述: IC BUS BUFF HOTSWAP 2WR 8MSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 緩沖器
Tx/Rx類型: I²C Logic
電容 - 輸入: 10pF
電源電壓: 2.3 V ~ 5.5 V
電流 - 電源: 4mA
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 帶卷 (TR)
配用: ISL33001MSOPEVAL1Z-ND - EVAL BOARD ISL33001 8MSOP
ISL33001, ISL33002, ISL33003
14
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7560.5
December 19, 2013
For additional products, see www.intersil.com/en/products.html
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
December 19, 2013
FN7560.5
Added Note 13 at the end of the "Elec Spec" table on page 5 as follows:
“13. If the Vcc1 and Vcc2 voltages diverge, then the shut-down Icc increases on the higher voltage
supply."
Added reference "(Note 13)" after "ISL33003 only" in rows for Vcc1 and Vcc2 "Shut-down Supply
current" parameters (last 2 rows of "Power Supplies" section) on page 4.
October 12, 2012
FN7560.4
Changed “SDA_IN, SCL_IN...0.3V to +(VCC1 + 0.3)V, SDA_OUT, SCL_OUT...0.3V to +(VCC2 + 0.3)V,
ENABLE, READY, ACC...0.3V to +(VCC1 + 0.3)V” to “SDA_IN, SCL_IN, SDA_OUT, SCL_OUT, READY...0.3V
to +7V; ENABLE, ACC...0.3V to +(VCC1 + 0.3)V”, in the Absolute Maximum Ratings section at the top of
Removed “Pb-free Reflow Profile” and link from “Thermal Information” section at the top of page 4.
Added “open drain” and “Connect to 10k pull-up resistor to VCC1.”, in Pin Descriptions in the READY
section on page 3.
10/11/11
FN7560.3
Converted to new datasheet template.
Changed Title of datasheet from: “2-Wire Bus Buffer With Rise Time Accelerators and Hot Swap
Capability”
to: I2C Bus Buffer with Rise Time Accelerators and Hot Swap Capability
Pg 1, added to Related Literature: AN1637, “Level Shifting Between 1.8V and 3.3V Using I2C Buffers”
Replaced POD M8.118 Rev 3 with Rev 4 due to the following changes:
Corrected lead width dimension in side view 1 from "0.25 - 0.036" to "0.25 - 0.36"
Replaced POD M8.15 Rev 1 with Rev 3 due to the following changes:
Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
Figure 3 (was Fig1) - Added:
- If tDELAY1 < tEN-LH then tDELAY2 = tEN-LH + tIDLE + tREADY-LH
- If tDELAY1 > tEN-LH then tDELAY2 = tEN-LH + tREADY-LH
and replaced graph
9/13/10
FN7560.2
Added SOIC package information to datasheet for ISL33001.
4/30/10
FN7560.1
Changed typical value of “Supply Current from VCC1” on page 4 for ISL33001 only from 2.2mA to
2.1mA.
Changed typical value of “Input-Output Offset Voltage” on page 5 from 100mV to 50mV.
3/18/10
FN7560.0
Initial Release.
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