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參數(shù)資料
| 型號： | ISL34341INZ-T13 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 0K |
| 描述： | IC VIDEO SERDES LONG 64-EPTQFP |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標準包裝： | 1,000 |
| 功能： | 串行器/解串器 |
| 輸入類型： | LVCMOS |
| 輸出類型： | LVCMOS |
| 輸入數(shù)： | 2 |
| 輸出數(shù)： | 2 |
| 電源電壓： | 1.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
1
FN6827.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL34341
WSVGA 24-Bit Long-Reach Video
SERDES with Bi-directional Side-Channel
The ISL34341 is a serializer/deserializer of LVCMOS parallel
video data. The video data presented to the serializer on the
parallel LVCMOS bus is serialized into a high-speed
differential signal. This differential signal is converted back to
parallel video at the remote end by the deserializer. It also
transports auxiliary data bi-directionally over the same link
during the video vertical retrace interval.
I2C bus mastering allows the placement of external slave
devices on the remote side of the link. An I2C controller can
be placed on either side of the link allowing bi-directional I2C
communication through the link to the external devices on
the other side. Both chips can be fully configured from a
single controller or independently by local controllers.
Ordering Information
Features
24-bit RGB transport over single differential pair
6MHz to 40MHz pixel clock rates
Bi-directional auxiliary data transport without extra
bandwidth and over the same differential pair
I2C Bus Mastering to the remote side of the link with a
controller on either the serializer or deserializer
40MHz PCLK transports
- SVGA 800x600 @ 70fps, 16% blanking
- WSVGA 1024x600 @ 60fps, 8% blanking
Internal 100
Ω termination on high-speed serial lines
DC balanced with industry standard 8b/10b line code
allows AC-coupling
- Provides immunity against ground shifts
Hot plugging with automatic resynchronization every line
16 programmable settings each for transmitter amplitude
boost and pre-emphasis and receiver equalization allow
for longer cable lengths and higher data rates
Programmable power-down of the transmitter and the
receiver
Same device for serializer and deserializer simplifies
inventory
I2C communication interface
8kV ESD rating for serial lines
Pb-free (RoHS compliant)
Applications
Navigation and display systems
Video entertainment systems
Industrial computing terminals
Remote cameras
PART
NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL34341INZ* ISL34341INZ -40 to +85 64 Ld EPTQFP Q64.10x10C
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
ISL34341
RG BA/B/C
PCLK_IN
RG BA/B/C
REF_CLK
PCLK_IN
VSYNC
HSYNC
DATAEN
PCLK_O UT
VSYNC
HSYNC
DATAEN
VI
D
E
O
_
T
X
I2
C
A
0
RE
F
_R
E
S
GND
_
CR
GND
_
P
GND
_
A
N
GND
_
TX
GND
_
CDR
GND
_
IO
VI
D
E
O
_
T
X
I2
C
A
0
RE
F
_R
E
S
GND
_
CR
GND
_
P
GND
_
A
N
GND
_
TX
GND
_
CDR
GND
_
IO
SERIO P
SERION
SERIO P
SERIO N
27nF
RS
TB
/P
DB
VD
D_
IO
VD
D_
CR
VDD
_
P
VDD
_AN
V
DD_
TX
VD
D_
CD
R
RS
TB
/P
DB
VD
D_
IO
VD
D_
CR
VDD
_
P
VDD
_AN
V
DD_
TX
VD
D_
CD
R
3.
16
K
Ω
3.
16
K
Ω
3.3V
1.8V
VDD_IO
3.3V
1.8V
VDD_IO
10m DIFFERENTIAL CABLE
24
VIDEO
SOURC E
VIDEO
SINK
VDD_IO
Data Sheet
October 8, 2010
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