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參數(shù)資料
| 型號(hào)： | ISL34341INZ-T13 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 10/11頁 |
| 文件大小： | 0K |
| 描述： | IC VIDEO SERDES LONG 64-EPTQFP |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 功能： | 串行器/解串器 |
| 輸入類型： | LVCMOS |
| 輸出類型： | LVCMOS |
| 輸入數(shù)： | 2 |
| 輸出數(shù)： | 2 |
| 電源電壓： | 1.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
8
FN6827.1
October 8, 2010
Applications
Overview
A pair of ISL34341 SERDES transports 24-bit parallel video
(16-bit parallel video for the ISL34321) along with auxiliary
data over a single 100
Ω differential cable either to a display
or from a camera. Auxiliary data is transferred in both
directions and can be used for remote configuration and
telemetry.
The benefits include lower EMI, lower costs, greater
reliability and space savings. The same device can be
configured to be either a serializer or deserializer by setting
one pin (VIDEO_TX), simplifying inventory. RGBA/B/C,
VSYNC, HSYNC, and DATAEN pins are inputs in serializer
mode and outputs in deserializer mode.
The video data presented to the serializer on the parallel
LVCMOS bus is serialized into a high-speed differential
signal. This differential signal is converted back to parallel
video at the remote end by the deserializer. The Side
Channel data is transferred between the SERDES pair
during two lines of the vertical video blanking interval.
When the side-channel is enabled, there will be a number of
PCLK cycles uncertainty from frame-to-frame. This should
not cause sync problems with most displays, as this occurs
during the vertical front porch of the blanking period. When
properly configured, the SERDES link supports end-to-end
transport with fewer than one error in 1010 bits.
Differential Signals and Termination
The ISL34341 serializes the 24-bit parallel data along with
3 sync signals at 30x the PCLK_IN frequency. The ISL34321
serializes the 16-bit parallel data plus 3 sync signals at 20x
the PCLK_IN frequency. The extra 2 bits per word come
from the 8b/10b encoding scheme which helps create the
highest quality serial link.
The high bit rate of the differential serial data requires
special care in the layout of traces on PCBs, in the choice
and assembly of connectors, and in the cables themselves.
PCB traces need to be adjacent and matched in length (so
as to minimize the imbalanced coupling to other traces or
elements) and of a geometry to match the impedance of the
transmitter and receiver to minimize reflections. Similar care
needs to be applied to the choice of connectors and cables.
SERIOP and SERION pins incorporate internal differential
termination of the serial signal lines.
SERIO Pin AC-Coupling
AC-coupling minimizes the effects of DC common mode
voltage difference and local power supply variations
between two SERDES. The serializer outputs DC balanced
8b/10b line code, which allows AC-coupling.
The AC-coupling capacitor on SERIO pins must be 27nF on
the serializer board and 27nF on the deserializer board. The
value of the AC-coupling capacitor is very critical since a
value too small will attenuate the high speed signal at low
clock rate. A value too big will slow down the turn around
time for the side-channel.
Receiver Reference Clock (REF_CLK)
The reference clock (REF_CLK) for the PLL is fed into
PCLK_IN pin. REF_CLK is used to recover the clock from
the high speed serial stream. REF_CLK is very sensitive to
any instability. The following conditions must be met at all
times after power is applied to the deserializer, or else the
deserializer may need a manual reset:
REF_CLK frequency must be within the limits specified
REF_CLK amplitude must be stable.
A simple 3.3V CMOS crystal oscillator can be used for
REF_CLK.
FIGURE 3. PARALLEL VIDEO OUTPUT TIMING [HSYNCPOL = 0, VSYNCPOL = 0, PCLKPOL (reg) = 0]
HSYNC
VSYNC
DATAEN
PCLK_OUT
RGB[A:C][7:0]
1/fOU
TODC
tOR
tDV
tOF
VALID DATA
DATA HELD AT PREVIOUS
VALID DATA
tDV
VIDEO_TX = 0
ISL34341
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