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參數(shù)資料
| 型號： | ISL36411DRZ-EVALZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR ISL36411DRZ |
| 標準包裝： | 1 |
| 系列： | * |
ISL36411
5
FN6965.1
March 25, 2010
Output Return Loss Limit
(Differential)
SDD22
100MHz to 4.1GHz
Note 7
dB
4.1MHz to 11.1GHz
Note 8
dB
Output Return Loss Limit
(Common Mode)
SCC22
100MHz to 2.5GHz
Note 9
dB
2.5MHz to 11.1GHz
-3
dB
Output Return Loss Limit
(Com. to Diff. Conversion)
SDC22
100MHz to 11.1GHz
-10
dB
Output Residual Jitter
10Gbps; Up to 10m 28AWG std twin-
axial cable (~ -27dB @ 5GHz);
1200mVP-P ≤ VIN ≤ 1600mVP-P
0.35
UI
Output Transition Time
tr, tf
20% to 80%
32
ps
Lane-to-Lane Skew
50
ps
Propagation Delay
From IN[k] to OUT[k]
500
ps
LOS Assert Time
Time to assert Loss-of-Signal indicator
when transitioning from active data
mode to line silence mode
50
s
LOS De-Assert Time
Time to assert Loss-of-Signal indicator
when transitioning from line silence
mode to active data mode
50
s
Data-to-Line Silence
Response Time
K28.5 data pattern at 10Gbps
100
s
Data-to-Line Silence
Response Time
K28.5 data pattern at 10Gbps
100
s
NOTES:
6. After channel loss, differential amplitudes at ISL36411 inputs must meet the input voltage range specified in “Absolute
7. Maximum Reflection Coefficient given by equation SDDXX(dB)= -12 + 2*√(f), with f in GHz. Established by characterization
and not production tested.
8. Maximum Reflection Coefficient given by equation SDDXX(dB)= -6.3+13Log10(f/5.5), with f in GHz. Established by
characterization and not production tested.
9. Reflection Coefficient given by equation SCCXX(dB) < -7 + 1.6*f, with f in GHz. Established by characterization and not
production tested.
10. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted
signal (as measured at the input to the channel). Total jitter (TJ) is DJPP + 14.1 x RJRMS.
11. Measured using a PRBS 27-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent,
media-induced loss only.
12. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
13. For active data mode, cable input amplitude is 300mVP-P (differential) or greater. For line silence mode, cable input amplitude
is 20mVP-P (differential) or less. Established by characterization and not production tested.
14. Limits established by characterization and are not production tested.
Electrical Specifications VDD = 1.2V, TA = +25°C, and VIN = 600mVP-P, unless otherwise noted. (Continued)
PARAMETERS
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
NOTES
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| ISL36411DRZ-T7 | 功能描述:接口 - 專用 ISL54100AHDMI EVAL BRD RHS CMPL 12 8LD RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| ISL36411DRZ-TS | 功能描述:接口 - 專用 ISL54065 EVALRD 1 SOCKET DGHTR BRD- 1 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| ISL3680 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Conversion Transceiver |
| ISL3680IR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Conversion Transceiver |
| ISL3680IR-TK | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Conversion Transceiver |
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