參數(shù)資料
型號(hào)： ISL41334EVAL1Z
廠(chǎng)商： Intersil
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 0K
描述： EVALUATION BOARD FOR ISL41334
產(chǎn)品培訓(xùn)模塊： Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，收發(fā)器，RS-232，RS-422，RS-485
嵌入式： 否
已用 IC / 零件： ISL41334
主要屬性： 2 個(gè)驅(qū)動(dòng)器，2 個(gè)接收器 - RS-232 模式
次要屬性： 1 個(gè)驅(qū)動(dòng)器，1 個(gè)接收器 - RS-422/RS-485 模式
已供物品： 板
17
FN6202.3
November 21, 2007
High ESD
All pins on the ISL81334, ISL41334 include ESD protection
structures rated at ±4kV (HBM), which is good enough to
survive ESD events commonly seen during manufacturing.
But the bus pins (Tx outputs and Rx inputs) are particularly
vulnerable to ESD events because they connect to an
exposed port on the exterior of the finished product. Simply
touching the port pins, or connecting a cable, can destroy an
unprotected port. ISL81334, ISL41334 bus pins are fitted
with advanced structures that deliver ESD protection in
excess of ±15kV (HBM), without interfering with any signal in
the RS-485 or the RS-232 range. This high level of
protection may eliminate the need for board level protection,
or at the very least will increase the robustness of any board
level scheme.
Small Packages
Many competing dual protocol ICs are available only in
monstrously large 24 to 28 Ld SOIC packages. The
ISL81334’s 28 Ld SSOP is 50% smaller than even a 24 Ld
SOIC, and the ISL41334’s tiny 6mmx6mm QFN is 80%
smaller than a 28 Ld SOIC.
Flow Through Pinouts
Even the ISL81334, ISL41334 pinouts are features, in that the
“flow-through” design simplifies board layout. Having the bus
pins all on one side of the package for easy routing to a cable
connector, and the Rx outputs and Tx inputs on the other side
for easy connection to a UART, avoids costly and problematic
crossovers. Figure 11 illustrates the flow-through nature of the
pinout.
Low Power Shutdown (SHDN) Mode
The ON/OFF pin is driven low to place the IC (both ports) in
the SHDN mode, and the already low supply current drops to
as low as 25A. If this functionality isn’t desired, the pin can
be left disconnected (thanks to the internal pull-up), or it
should be connected to VCC (VL for the QFN), through a
1k
Ω resistor. SHDN disables the Tx and Rx outputs, and
disables the charge pumps if either port is in RS-232 mode,
so V+ collapses to VCC, and V- collapses to GND.
All but 5A of SHDN ICC current is due to control input (ON,
LB, SP, DE) pull-up resistors (~20A/resistor), so SHDN ICC
varies depending on the ISL81334, ISL41334 configuration.
The specification tables indicate the worst case values, but
careful selection of the configuration yields lower currents.
For example, in RS-232 mode the SP pins aren’t used, so if
both ports are configured for RS-232, floating or tying the SP
pins high minimizes SHDN ICC. Likewise in RS-485 mode,
the drivers are disabled in SHDN, so driving the DE pins
high during this time also reduces ICC.
On the ISL41334, the SHDN ICC increases as VL decreases.
VL powers the input stage and sets its VOH at VL rather than
VCC. VCC powers the second stage, but the second stage
input isn’t driven to the rail, so some ICC current flows. See
Figure 21 for details.
When enabling from SHDN in RS-232 mode, allow at least
20s for the charge pumps to stabilize before transmitting
data. The charge pumps aren’t used in RS-485 mode, so the
transceiver is ready to send or receive data in less than 1s,
which is much faster than competing devices that require the
charge pump for all modes of operation.
Internal Loopback Mode
Driving the LB pin low places both ports in the loopback
mode, a mode that facilitates implementing board level self
test functions. In loopback, internal switches disconnect the
Rx inputs from the Rx outputs, and feed back the Tx outputs
to the appropriate Rx output. This way the data driven at the
Tx input appears at the corresponding Rx output (refer to
remain connected to their terminals, so the external loads
are reflected in the loopback performance. This allows the
loopback function to potentially detect some common bus
faults such as one or both driver outputs shorted to GND, or
outputs shorted together.
Note that the loopback mode uses an additional set of
These loopback receivers are not standards compliant, so
the loopback mode can’t be used to implement a half-duplex
RS-485 transceiver.
If loopback won’t be utilized, the pin can be left disconnected
(thanks to the internal pull-up), or it should be connected to
VCC (VL for the QFN), through a 1kΩ resistor.
ISL41334 (QFN Package) Special Features
Logic Supply (VL Pin)
The ISL41334 (QFN) includes a VL pin that powers the logic
inputs (Tx inputs and control pins) and Rx outputs. These
pins interface with “l(fā)ogic” devices such as UARTs, ASICs,
and controllers, and today most of these devices use power
supplies significantly lower than 5V. Thus, a 5V output level
from a 5V powered dual protocol IC might seriously
overdrive and damage the logic device input. Similarly, the
UART
OR
ASIC
OR
CONTROLLER
RA2
DY2
RA1
DY1
Z2
Y2
Y1
Z1
A1
B1
A2
B2
CON
N
E
C
T
O
R
ISL81334
FIGURE 11. ILLUSTRATION OF FLOW THROUGH PINOUT
D
R
ISL81334, ISL41334
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