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參數(shù)資料
| 型號(hào)： | ISL43L841IRZ-T |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX/DEMUX 4X1 16TQFN |
| 標(biāo)準(zhǔn)包裝： | 6,000 |
| 功能： | 多路復(fù)用器/多路分解器 |
| 電路： | 1 x 4:1 |
| 導(dǎo)通狀態(tài)電阻： | 480 毫歐 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 1.65 V ~ 4.5 V |
| 電流 - 電源： | 20nA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-WFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 16-QFN-EP（3x3） |
| 包裝： | 帶卷 (TR) |
6
FN6212.1
June 30, 2006
Test Circuits and Waveforms
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. INHIBIT tON/tOFF MEASUREMENT POINTS
Repeat test for other switches. CL includes fixture and stray
capacitance.
FIGURE 1B. INHIBIT tON/tOFF TEST CIRCUIT
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS
Repeat test for other switches. CL includes fixture and stray
capacitance.
FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
FIGURE 2A. Q MEASUREMENT POINTS
FIGURE 2B. Q TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
50%
tr < 5ns
tf < 5ns
tON
V+
0V
tOFF
LOGIC
INPUT
SWITCH
OUTPUT
90%
0V
90%
VOUT
VA0, VB0
V
OUT
V
(NO or NC)
R
L
R
L
R
ON
()
+
------------------------------
=
LOGIC
INPUT
VOUT
RL
COMA
A0, B0
INH
50
35pF
GND
A1, A2, B1,
CL
V+
ADD0-1
C
V+
C
B2, A3, B3
COMB
50%
tr < 5ns
tf < 5ns
tTRANS
90%
V+
VA3, VB3
0V
tTRANS
LOGIC
INPUT
SWITCH
OUTPUT
10%
VOUT
VA0, VB0
0V
V
OUT
V
(NO or NC)
R
L
R
L
R
ON
()
+
------------------------------
=
LOGIC
INPUT
VOUT
RL
COMA,
A0, B0
ADD0-1
50
35pF
GND
A1, A2, B1,
CL
V+
INH
C
V+
C
B2, A3, B3
COMB
VOUT
OFF
ON
OFF
Q =
VOUT x CL
SWITCH
OUTPUT
LOGIC
INPUT
V+
0V
CL
VOUT
RG
VG
GND
COMA,
Ax, Bx
LOGIC
INPUT
INH
ADD1
V+
C
Repeat test for other switches.
1000pF
0
COMB
ADD0
CHANNEL
SELECT
ISL43L841
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