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參數(shù)資料
| 型號： | ISL54505IHZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH SPDT SOT23-6 |
| 標準包裝： | 3,000 |
| 功能： | 開關(guān) |
| 電路： | 1 x SPST- NC |
| 導通狀態(tài)電阻： | 2.5 歐姆 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 1.8 V ~ 5.5 V |
| 電流 - 電源： | 28nA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應商設(shè)備封裝： | SOT-23-6 |
| 包裝： | 帶卷 (TR) |
7
FN6552.2
October 23, 2009
Detailed Description
The ISL54504 and ISL54505 are bidirectional, single
pole/single throw (SPST) analog switches. They offer
precise switching capability from a single 1.8V to 5.5V
supply with low ON-resistance (2.5Ω) and high speed
operation (tON = 25ns, tOFF = 15ns). The devices are
especially well suited for portable battery powered
equipment due to their low operating supply voltage
(1.8V), low power consumption (0.15W), low
leakage currents (300nA max) and tiny TDFN and
SOT-23 packages.
The ISL54504 is a single normally open (NO) SPST
analog switch. The ISL54505 is a single normally
closed (NC) SPST analog switch.
External V+ Series Resistor
For improved ESD and latch-up immunity, Intersil
recommends adding a 100Ω resistor in series with the
V+ power supply pin of the ISL54504, ISL54505 IC
(see Figure 6).
During an overvoltage transient event (such as occurs
during system level IEC 61000 ESD testing), substrate
currents can be generated in the IC that can trigger
parasitic SCR structures to turn ON, creating a low
impedance path from the V+ power supply to ground.
This will result in a significant amount of current flow in
the IC, which can potentially create a latch-up state or
permanently damage the IC. The external V+ resistor
limits the current during this over-stress situation and
has been found to prevent latch-up or destructive
damage for many overvoltage transient events.
Under normal operation the sub-microamp IDD current
of the IC produces an insignificant voltage drop across
the 100Ω series resistor resulting in no impact to
switch operation or performance.
Supply Sequencing And Overvoltage
Protection
With any CMOS device, proper power supply
sequencing is required to protect the device from
excessive input currents, which might permanently
damage the IC. All I/O pins contain ESD protection
diodes from the pin to V+ and to GND (see Figure 7).
To prevent forward biasing these diodes, V+ must be
applied before any input signals, and the input signal
voltages must remain between V+ and GND.
If these conditions cannot be guaranteed then
precautions must be implemented to prohibit the
current and voltage at the logic pin and signal pins
from exceeding the maximum ratings of the switch.
The following two methods can be used to provide
additional protection to limit the current in the event
that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 7). The
resistor limits the input current below the threshold
that produces permanent damage and the sub-
FIGURE 5. CAPACITANCE TEST CIRCUIT
Test Circuits and Waveforms (Continued)
V+
C
GND
NO OR NC
COM
IN
IMPEDANCE
ANALYZER
VINL OR VINH
FIGURE 6. V+ SERIES RESISTOR FOR ENHANCED
ESD AND LATCH-UP IMMUNITY
IN
COM
100Ω
NO
NC
V+
GND
C
OPTIONAL
PROTECTION
RESISTOR
ISL54504, ISL54505
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