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| 型號(hào)： | ISL55210IRTZ-T7 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 8/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP DIFF 2200MHZ LP 16TQFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 放大器類型： | 差分 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分 |
| 轉(zhuǎn)換速率： | 5600 V/µs |
| 增益帶寬積： | 4GHz |
| -3db帶寬： | 2.2GHz |
| 電流 - 輸入偏壓： | 50µA |
| 電壓 - 輸入偏移： | 100µV |
| 電流 - 電源： | 35mA |
| 電流 - 輸出 / 通道： | 45mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 4.2 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 16-TQFN（3x3） |
| 包裝： | 帶卷 (TR) |
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ISL55210
16
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7811.2
June 6, 2013
For additional products, see www.intersil.com/en/products.html
Layout Considerations
The ISL55210 pinout is organized to isolate signal I/O along one
axis of the package with ground, power and control pins on the
other axis. Ground and power should be planes coming into the
upper and lower sides of the package (see the Pin Configuration
on page 2). The signal I/O should be laid out as tight as possible
with parasitic C to the ground and/or power planes reduced as
much as possible by opening up those planes under the I/O
elements.
The ground pins and package backside metal contact should be
connected into a good ground plane. The power supply should
have both a large value electrolytic cap to ground, then a high
frequency ferrite beads, then 0.01F SMD ceramic caps at the
supply pins. Some improvement in HD2 performance may be
experienced by placing and X2Y cap between the two VS+ pins
and ground underneath the package on the board back side. This
is 4 terminal device that is included in the EVM board layout.
EVM Board (Rev. C)
Test circuit #1 (Figure 28) is implemented on an Evaluation
Module Board available from Intersil. This board includes a
number of optional features that are not populated as the board
is delivered. The full EVM board circuit is shown in Figure 38
where unloaded (optional) elements are shown in green.
The nominal supply voltage for the board and device is a single
3.3V supply. From this, the ISL55210, ISL55211 generates an
internal common mode voltage of approximately 1.2V. That
voltage can be overridden by populating the two resistors and
potentiometer shown as R19 to R21 above.
The primary test purpose for this board is to implement different
interstage differential passive filters intended for the ADC
interface along with the ADC input impedances. The board is
delivered with only the output R's loaded to give a 200
differential load. This is done using the two 85 resistors as R9
and R10, then the 4 zero ohm elements (R10, R12, R24, and R25)
and finally the two shunt elements R13 and R14 set to 35.5.
Including the 50 measurement load on the output side of the 1:1
transformer reflecting in parallel with the two 35 resistors takes
the nominal AC shunt impedance to 71||50 = 29.3. This adds
to the two 85 series output elements to give a total load across
the amplifier outputs of 170 + 29.3 = 199.3.
To test a particular ADC interface RLC filter and converter input
impedance, replace R11 and R12 with RF chip inductors, load
C10 and C11 with the specified ADC input capacitance and R26
with the specified ADC differential input R. With these loaded,
the remaining resistive elements (R24, R25, R13, R14) are set to
hit a desired total parallel impedance to implement the desired
filter (must be < than the ADC input differential R since that sits
in parallel with any "external" elements) and achieve a 25
source looking into each side of the tap point transformer.
This EVM board includes a user's manual showing a number of
example circuits and tested results. Available on the Intersil web
site in the ISL55210 Product Information Page.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
June 6, 2013
FN7811.2 Added Related Literature on page 1.
Updated Figure “NOISE MODEL AND TEST CIRCUIT” on page 14 that was incorrectly drawn.
July 30, 2012
FN7811.1 Added 6th paragraph to section “Power Supply, Shutdown, and Thermal Considerations” on page 13 describing the
outputs can not source or sink current during disable mode.
March 2, 2011
FN7811.0 Initial Release
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