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參數(shù)資料
| 型號： | ISL6316CRZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Quadruple 2-Input Exclusive-OR Gates 14-PDIP -40 to 85 |
| 中文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, PLASTIC, MO-220-VJJD-2, QFN-40 |
| 文件頁數(shù)： | 12/29頁 |
| 文件大?。?/td> | 838K |
| 代理商： | ISL6316CRZ-T |
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12
FN9227.0
August 31, 2005
previous phase. The peak-to-peak current for each phase is
about 7A, and the dc components of the inductor currents
combine to feed the load.
To understand the reduction of ripple current amplitude in the
multiphase circuit, examine the equation representing an
individual channel’s peak-to-peak inductor current.
In Equation 1, V
IN
and V
OUT
are the input and output
voltages respectively, L is the single-channel inductor value,
and f
S
is the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each of
the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output-
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
Another benefit of interleaving is to reduce input ripple current.
Input capacitance is determined in part by the maximum input
ripple current. Multiphase topologies can improve overall
system cost and size by lowering input ripple current and
allowing the designer to reduce the cost of input capacitance.
The example in Figure 2 illustrates input currents from a three-
phase converter combining to reduce the total input ripple
current.
The converter depicted in Figure 2 delivers 36A to a 1.5V load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has 11.9A
RMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent three-phase converter.
Figures 21, 22 and 23 in the section entitled
Input Capacitor
Selection
can be used to determine the input-capacitor RMS
current based on load current, duty cycle, and the number of
channels. They are provided as aids in determining the
optimal input capacitor solution. Figure 24 shows the single
phase input-capacitor RMS current for comparison.
PWM Operation
The timing of each channel is set by the number of active
channels. The default channel setting for the ISL6316 is four.
The switching cycle is defined as the time between PWM
pulse termination signals of each channel. The pulse
termination signal is an internally generated clock signal
which triggers the falling edge of PWM signal. The cycle time
of the pulse termination signal is the inverse of the switching
frequency set by the resistor between the FS pin and ground.
Each cycle begins when the clock signal commands the
channel PWM signal to go low. The PWM signals command
the MOSFET driver to turn on/off the channel MOSFETs.
For 4-channel operation, the channel firing order is 4-3-2-1:
PWM3 pulse terminates 1/4 of a cycle after PWM4, PWM2
output follows another 1/4 of a cycle after PWM3, and PWM1
terminates another 1/4 of a cycle after PWM2. For 3-channel
operation, the channel firing order is 3-2-1.
Connecting PWM4 to VCC selects three channel operation
and the pulse-termination times are spaced in 1/3 cycle
increments. If PWM3 is connected to VCC, two channel
operation is selected and the PWM2 pulse terminates 1/2 of a
cycle later.
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
1μs/DIV
PWM2, 5V/DIV
PWM3, 5V/DIV
IL2, 7A/DIV
IL3, 7A/DIV
IL1 + IL2 + IL3, 7A/DIV
IL1, 7A/DIV
PWM1, 5V/DIV
I
P-P
V
----------------------------------- V
V
Lf
S
V
IN
(
OUT
=
(EQ. 1)
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-
CAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
CHANNEL 3
INPUT CURRENT
10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
INPUT-CAPACITOR CURRENT, 10A/DIV
1μs/DIV
I
C P-P
,
V
------------------------------------------- V
N V
Lf
S
V
IN
(
OUT
=
(EQ. 2)
ISL6316
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